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AgeCommit message (Expand)AuthorFilesLines
2018-04-05Use dlsym to check if libdl is needed for pluginH.J. Lu1-0/+5
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu1-0/+7
2018-03-30Make power8 the default cpu when assembling for 64-bit little endian targets.Peter Bergner1-0/+6
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li1-0/+35
2018-03-28x86: drop VecESizeJan Beulich1-0/+12
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-0/+9
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-0/+5
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich1-0/+6
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+9
2018-03-22x86: use local variable in check_VecOperands()Jan Beulich1-0/+5
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich1-0/+8
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-0/+7
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-0/+8
2018-03-22x86: fold a few XOP templatesJan Beulich1-0/+7
2018-03-19Updated Spanish translation for the bfd/ sub-directory, and updated Ukranian ...Nick Clifton1-0/+4
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson1-0/+9
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+19
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton1-0/+4
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu1-0/+7
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu1-0/+7
2018-03-08x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu1-0/+20
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-0/+7
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-0/+20
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-0/+8
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-0/+5
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-0/+8
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich1-0/+8
2018-03-08x86: fold redundant expressions in process_suffix()Jan Beulich1-0/+5
2018-03-08x86: simplify result processing of cpu_flags_match()Jan Beulich1-0/+5
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich1-0/+22
2018-03-08x86: change AVX512VL handling in cpu_flags_match()Jan Beulich1-0/+4
2018-03-08x86: drop CPU_FLAGS_32BIT_MATCHJan Beulich1-0/+6
2018-03-08x86: simplify AVX checks in cpu_flags_match()Jan Beulich1-0/+8
2018-03-08x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCHJan Beulich1-0/+5
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich1-0/+20
2018-03-08x86: drop FloatDJan Beulich1-0/+5
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich1-0/+5
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich1-0/+8
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich1-0/+6
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-0/+5
2018-03-08Really remove unnecessary power9 group terminating nopAlan Modra1-0/+6
2018-03-08Remove unnecessary power9 group terminating nopAlan Modra1-0/+5
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu1-0/+97
2018-03-07XCOFF disassemblerAlan Modra1-0/+6
2018-03-02[ARM] Fix NULL dereference of march_ext_optThomas Preud'homme1-0/+5
2018-03-01[ARM] Clean up selection of feature bitsThomas Preud'homme1-0/+44
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-0/+10
2018-03-01Add missing translations to ALL_LINGUASAlan Modra1-0/+5
2018-02-27gas: Rename .nop directive to .nopsH.J. Lu1-0/+33
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+36
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