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AgeCommit message (Expand)AuthorFilesLines
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist1-0/+23
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-0/+7
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-0/+9
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-0/+5
2017-11-23x86: correct UDnJan Beulich1-0/+9
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich1-0/+7
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+21
2017-11-22Update docs on filling text with nops.Jim Wilson1-0/+5
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme1-0/+7
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss1-0/+4
2017-11-21x86: Add tests for -n option of x86 assemblerH.J. Lu1-0/+8
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss1-0/+25
2017-11-21xtensa error messageAlan Modra1-0/+5
2017-11-21mingw gas testsuite fixAlan Modra1-0/+4
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+7
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-0/+7
2017-11-16Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina1-0/+5
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-0/+15
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich1-0/+6
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-0/+9
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu1-0/+5
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-0/+10
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton1-0/+17
2017-11-15x86: use correct register namesJan Beulich1-0/+6
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich1-0/+5
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich1-0/+12
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson1-0/+4
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich1-0/+5
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-0/+8
2017-11-14x86: string insns don't allow displacementsJan Beulich1-0/+9
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich1-0/+5
2017-11-13gas/ia64: fix testsuite failuresJan Beulich1-0/+6
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-0/+7
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich1-0/+8
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich1-0/+11
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson1-0/+4
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina1-0/+5
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina1-0/+8
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+9
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+5
2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-0/+6
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang1-0/+32
2017-11-08xtensa message pluralizationAlan Modra1-0/+4
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson1-0/+8
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt1-0/+7
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina1-0/+6
2017-11-07bundle_lock message tidyAlan Modra1-0/+6
2017-11-07readelf ngettext fixesAlan Modra1-0/+35
2017-11-07gas and ld pluralization fixesAlan Modra1-0/+20
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