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2024-06-10autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCEMatthieu Longo1-1/+0
- AC_AIX, AC_MINIX, and AC_GNU_SOURCE by AC_USE_SYSTEM_EXTENSIONS https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fAIX https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fMINIX-1 https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.72/autoconf.html#index-AC_005fGNU_005fSOURCE-1
2024-06-09Automatic date update in version.inGDB Administrator1-1/+1
2024-06-08Automatic date update in version.inGDB Administrator1-1/+1
2024-06-07Re: Yet another ecoff fuzzed object fixAlan Modra1-0/+1
In commit 6fc018e9e593 I replaced the fdr_ptr csym check against the header isymMax count with a check against bfd symcount. In fact, both checks are needed. The isymMax check sanity checks accesses against the external sym array, the symcount one against the internal array. * ecoff.c (_bfd_ecoff_slurp_symbol_table): Reinstate fdr_ptr csym check against isymMax.
2024-06-07aarch64: Fix DT_RELR support with discarded sectionsSzabolcs Nagy1-2/+3
In case of discarded sections, via /DISCARD/ or .gnu.linkonce, relr relocation accounting was wrong. This broke building linux. The issue was that the *_relocate_section logic was copied to record_relr_non_got_relocs to find the relative relocs that can be packed, however *_relocate_section is not called on sections that are discarded, while record_relr_non_got_relocs is called for all input sections. The fix is to filter out the discarded sections with the same logic that is used to count non-GOT relocs in *_late_size_sections for local symbols earlier. Use the discarded_section helper in both cases to clarify the intent and handle all corner-cases consistently. GOT relocations are affected too if all sections are discarded that reference the GOT entry of a particular symbol, however this can cause unused GOT entries independently of DT_RELR, and the only difference with DT_RELR is that a relative reloc may be emitted instead of a R_AARCH64_NONE for the unused GOT entry which is acceptable. A proper fix would require redoing the GOT refcounting after we know the discarded sections, see bug 31850.
2024-06-07Automatic date update in version.inGDB Administrator1-1/+1
2024-06-06Updated Spanish translation for the bfd/ directoryNick Clifton1-852/+536
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+7
This implements the Zvfbfwma extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin 2 Depending on different usage scenarios, the Zvfbfwma extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. This is consistent with the processing strategy in Zvfbfmin. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfwma.d: New test. * testsuite/gas/riscv/zvfbfwma.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. (MASK_VFWMACCBF16_VF): Ditto. (MATCH_VFWMACCBF16_VV): Ditto. (MASK_VFWMACCBF16_VV): Ditto. (DECLARE_INSN): New declarations for Zvfbfwma. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFWMA opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+6
This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts> Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin.d: New test. * testsuite/gas/riscv/zvfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions.
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+6
This implements the Zfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc> 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions.
2024-06-06Automatic date update in version.inGDB Administrator1-1/+1
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a ↵Nick Clifton1-10/+34
NULL section pointer. PR 31843
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+5
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVelw as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-elw-fail.d: New test. * testsuite/gas/riscv/cv-elw-fail.l: New test. * testsuite/gas/riscv/cv-elw-fail.s: New test. * testsuite/gas/riscv/cv-elw-fail-march.d: New test. * testsuite/gas/riscv/cv-elw-fail-march.l: New test. * testsuite/gas/riscv/cv-elw-fail-march.s: New test. * testsuite/gas/riscv/cv-elw-pass.d: New test. * testsuite/gas/riscv/cv-elw-pass.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvelw string. opcodes/ChangeLog: * riscv-opc.c: (riscv_opcode) Add event load instructions. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction opcode macros. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-06-05Automatic date update in version.inGDB Administrator1-1/+1
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang4-29/+1
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only created at the first time to handle alignment directive. This means that all other sections may use this symbol. If the section of this symbol is discarded, there may be problems. Search it in its own section. Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. Co-authored-by: Jinyang He <hejinyang@loongson.cn> Reported-by: WANG Xuerui <git@xen0n.name> Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-06-04Automatic date update in version.inGDB Administrator1-1/+1
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2024-05-31aarch64: Add DT_RELR supportSzabolcs Nagy2-1/+439
The logic to decide if an input relocation for a symbol becomes a particular kind of output relocation is one of the hard to maintain parts of the bfd ld backend, since it is partially repeated across elfNN_aarch64_check_relocs (where dynamic relocations are counted per symbol and input section), elfNN_aarch64_late_size_sections (where relocation sections are sized and GOT offsets assigned), elfNN_aarch64_relocate_section (where most relocations are applied and output to a relocation section), elfNN_aarch64_finish_dynamic_symbol (where some of the GOT relocations are applied and output). The DT_RELR support adds another layer to this complexity: after the output relocation sections are sized, so all dynamic relocations are accounted (in elfNN_aarch64_late_size_sections), we scan the symbols and input relocations again to decide which ones become relative relocations that can be packed. The sizes of the relocation sections are updated accordingly. This logic must be consistent with the code that applies the relocs later so each relative relocation is emitted exactly once: either in .rela.* or packed in .relr.dyn. Sizing of .relr.dyn is done via elfNN_aarch64_size_relative_relocs that may be called repeatedly whenever the layout changes since an address change can affect the size of the packed format. Then the final content is emitted in elfNN_aarch64_finish_relative_relocs, that is called after the layout is final and before relocations are applied and emitted. These hooks are only called if DT_RELR is enabled. We only pack relative relocs that are known to be aligned in the output during .relr.dyn sizing, the potentially unaligned relative relocs are emitted normally (in .rela.*, not packed), because the format requires aligned addresses.
2024-05-31Automatic date update in version.inGDB Administrator1-1/+1
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2024-05-28Updated Spanish translation for the BFD sub-directory.Nick Clifton1-4754/+7118
2024-05-28Automatic date update in version.inGDB Administrator1-1/+1
2024-05-28RISC-V: Fixed overwritten IRELATIVE relocs in the .rel.iplt for data reloc.Nelson Chu1-6/+16
This was originally reported by Hau Hsu <hau.hsu@sifive.com>. Similar to commit 51a8a7c2e3cc0730831963651a55d23d1fae624d We shouldn't use riscv_elf_append_rela to add dynamic relocs into .rela.iplt in the riscv_elf_relocate_section when handling ifunc data reloc R_RISCV_32/64. This just like what did in the riscv_elf_finish_dynamic_symbol. bfd/ * elfnn-riscv.c (riscv_elf_relocate_section): We shouldn't use riscv_elf_append_rela to add dynamic relocs into .rela.iplt in the riscv_elf_relocate_section when handling ifunc data reloc. ld/ * testsuite/ld-riscv-elf/ifunc-overwrite.s: Updated and renamed. * testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-overwrite.d: Renamed.
2024-05-28RISC-V: Segment fault for kernel purgatory when linking.Nelson Chu1-13/+10
This was originally reported by Ard Biesheuvel <ardb@kernel.org>. The followings are reproduce steps, https://lore.kernel.org/all/202404260640.9GQVTmrw-lkp@intel.com/T/#u The segment fault happens in the riscv_elf_finish_dynamic_sections when the output got section is an ABS. Refer to MIPS code, they added an extra bfd_is_abs_section check to avoid ABS got, so this seems the right and easier way to go in the short-term. bfd/ * elfnn-riscv.c (riscv_elf_finish_dynamic_sections): Set sh_entsize and fill the got entries only when the got isn't an ABS section, and the size of got is larger than zero. The similar goes for gotplt, except we already reported error when the gotplt is an ABS.
2024-05-27LoongArch: Fix relaxation overflow caused by ld -z separate-codemengqinggang1-39/+62
ld -z separate-code let .text and .rodata in two different but read only segment. If the symbol and pc in two segment, the offset from pc to symbol need to consider segment alignment. Add a function 'loongarch_two_sections_in_same_segment' to determine whether two sections are in the same segment.
2024-05-27Automatic date update in version.inGDB Administrator1-1/+1
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2024-05-17bfd: sframe: minor code adjustments and fix typosIndu Bhagat1-7/+5
bfd/ * elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Use local variable. (_bfd_x86_elf_size_dynamic_sections): Fix typos.
2024-05-17Automatic date update in version.inGDB Administrator1-1/+1
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2024-05-14Improve objdump -p output of PE Import and Export TablesPali Roh?r1-23/+38
PR 31738
2024-05-14arm: remove Maverick support from BFD.Richard Earnshaw2-74/+22
Remove the handling of Maverick from BFD. Where appropriate we handle legacy code by mapping ep9312 onto Armv4t.
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2024-05-12Automatic date update in version.inGDB Administrator1-1/+1
2024-05-11Automatic date update in version.inGDB Administrator1-1/+1
generated by cgit v1.1 at 2024-09-07 16:12:05 +0000