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2017-07-19[ARC] Add JLI support.John Eric Martin1-0/+1
The following relocation types were added to GCC/binutils: ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by GCC as well to adjust the index of function calls to functions with attribute jli_call_always. bfd/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c (JLI): Define. * reloc.c: Add JLI relocations. gas/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/jli-1.d: New file. * testsuite/gas/arc/jli-1.s: Likewise. * testsuite/gas/arc/taux.d: Update for jli_base. include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * elf/arc-reloc.def: Add JLI relocs howto. * opcode/arc-func.h (replace_jli): New function. ld/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * emulparams/arcelf.sh (JLI_START_TABLE): Define. * scripttempl/elfarc.sc: Handle jlitab section. * scripttempl/elfarcv2.sc: Likewise. * testsuite/ld-arc/arc.exp: Add JLI test. * testsuite/ld-arc/jli-script.ld: New file. * testsuite/ld-arc/jli-simple.dd: Likewise. * testsuite/ld-arc/jli-simple.rd: Likewise. * testsuite/ld-arc/jli-simple.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * arc-opc.c (UIMM10_6_S_JLIOFF): Define. (UIMM3_23): Adjust accordingly. * arc-regs.h: Add/correct jli_base register. * arc-tbl.h (jli_s): Likewise.
2017-06-28Change bfd_get_size/bfd_get_file_size to ufile_ptrH.J. Lu1-2/+2
bfd_get_size and bfd_get_file_size should return the unsigned file size. Otherwise they return negative values for file >= 2GB with 32-bit ufile_ptr. bfd/ * bfd-in2.h: Regenerated. * bfdio.c (bfd_get_size): Change return type to ufile_ptr. (bfd_get_file_size): Likewise. binutils/ * objdump.c (dump_relocs_in_section): Cast to ufile_ptr when comparing against bfd_get_file_size return.
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+1
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-26RISC-V: Use pc-relative relocation for FDE initial locationKuan-Lin Chen1-0/+1
The symbol address in .eh_frame may be adjusted in _bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert a relocation whose addend symbol is in .eh_frame. Othrewise, the value may be adjusted twice. bfd/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elfnn-riscv.c (perform_relocation): Support the new R_RISCV_32_PCREL relocation. (riscv_elf_relocate_section): Likewise. * elfxx-riscv.c (howto_table): Likewise. (riscv_reloc_map): Likewise. * bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation. * libbfd.h: Regenerate. gas/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a R_RISCV_32_PCREL relocation. include/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elf/riscv.h (R_RISCV_32_PCREL): New.
2017-06-23[AArch64] Fix typo in comments on relocation nameJiong Wang1-2/+2
BFD_RELOC_AARCH64_ADR_GOTPAGE should be BFD_RELOC_AARCH64_ADR_GOT_PAGE. bfd/ * reloc.c (BFD_RELOC_AARCH64_ADR_GOTPAGE): Rename to BFD_RELOC_AARCH64_ADR_GOT_PAGE * bfd-in2.h: Regenerated.
2017-06-16Rewrite __start and __stop symbol handlingAlan Modra1-1/+14
This arranges for __start and __stop symbols to be defined before garbage collection, for all target formats. That should allow the COFF and PE --gc-sections to keep a singleton orphan input section, a feature lost by 2017-06-13 commit cbd0eecf26. The fancier ELF treatment of keeping all input sections associated with a __start or __stop symbol, from 2015-10-23 commit 1cce69b9dc, is retained. .startof. and .sizeof. symbols are deliberately not defined before garbage collection, so these won't affect garbage collection of sections. The patch also ensures __start, __stop, .startof. and .sizeof. symbols are defined before target size_dynamic_sections is called, albeit with a preliminary value, so that target code doesn't need to cope with a symbol changing from undefined at size_dynamic_sections to defined at relocate_section. Also, a number of problems with the testcases have been fixed. PR ld/20022 PR ld/21557 PR ld/21562 PR ld/21571 include/ * bfdlink.h (struct bfd_link_hash_entry): Delete undef.section. bfd/ * targets.c (struct bfd_target): Add _bfd_define_start_stop. (BFD_JUMP_TABLE_LINK): Likewise. * elf-bfd.h (bfd_elf_define_start_stop): Declare. * elflink.c (_bfd_elf_gc_mark_rsec): Update comment. (bfd_elf_define_start_stop): New function. * linker.c (bfd_generic_define_start_stop): New function. * coff64-rs6000.c (rs6000_xcoff64_vec, rs6000_xcoff64_aix_vec): Init new field. * aout-adobe.c (aout_32_bfd_define_start_stop): Define. * aout-target.h (MY_bfd_define_start_stop): Define. * aout-tic30.c (MY_bfd_define_start_stop): Define. * binary.c (binary_bfd_define_start_stop): Define. * bout.c (b_out_bfd_define_start_stop): Define. * coff-alpha.c (_bfd_ecoff_bfd_define_start_stop): Define. * coff-mips.c (_bfd_ecoff_bfd_define_start_stop): Define. * coff-rs6000.c (_bfd_xcoff_bfd_define_start_stop): Define. * coffcode.h (coff_bfd_define_start_stop): Define. * elfxx-target.h (bfd_elfNN_bfd_define_start_stop): Define. * i386msdos.c (msdos_bfd_define_start_stop): Define. * i386os9k.c (os9k_bfd_define_start_stop): Define. * ieee.c (ieee_bfd_define_start_stop): Define. * ihex.c (ihex_bfd_define_start_stop): Define. * libbfd-in.h (_bfd_nolink_bfd_define_start_stop): Define. * mach-o-target.c (bfd_mach_o_bfd_define_start_stop): Define. * mmo.c (mmo_bfd_define_start_stop): Define. * nlm-target.h (nlm_bfd_define_start_stop): Define. * oasys.c (oasys_bfd_define_start_stop): Define. * pef.c (bfd_pef_bfd_define_start_stop): Define. * plugin.c (bfd_plugin_bfd_define_start_stop): Define. * ppcboot.c (ppcboot_bfd_define_start_stop): Define. * som.c (som_bfd_define_start_stop): Define. * srec.c (srec_bfd_define_start_stop): Define. * tekhex.c (tekhex_bfd_define_start_stop): Define. * versados.c (versados_bfd_define_start_stop): Define. * vms-alpha.c (vms_bfd_define_start_stop): Define. (alpha_vms_bfd_define_start_stop): Define. * xsym.c (bfd_sym_bfd_define_start_stop): Define. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Don't set __start/__stop syms here. * ldlang.c (lang_set_startof): Delete. (start_stop_syms, start_stop_count, start_stop_alloc): New vars. (lang_define_start_stop, lang_init_start_stop, foreach_start_stop, undef_start_stop, lang_undef_start_stop, lang_init_startof_sizeof, set_start_stop, lang_finalize_start_stop): New functions. (lang_process): Call _start_stop functions. * testsuite/ld-elf/pr21562a.d: Use xfail rather than notarget. Correct typos and list of xfail targets. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562e.d: Likewise. * testsuite/ld-elf/pr21562f.d: Likewise. * testsuite/ld-elf/pr21562g.d: Likewise. * testsuite/ld-elf/pr21562h.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/sizeofa.d: Likewise. Adjust to pass for generic ELF. * testsuite/ld-elf/sizeofb.d: Likewise. * testsuite/ld-elf/startofa.d: Likewise. * testsuite/ld-elf/startofb.d: Likewise.
2017-05-30Add bfd_get_file_size to get archive element sizeH.J. Lu1-0/+2
We can't use stat() to get archive element size. Add bfd_get_file_size to get size for both normal files and archive elements. bfd/ PR binutils/21519 * bfdio.c (bfd_get_file_size): New function. * bfd-in2.h: Regenerated. binutils/ PR binutils/21519 * objdump.c (dump_relocs_in_section): Replace get_file_size with bfd_get_file_size to get archive element size. * testsuite/binutils-all/objdump.exp (test_objdump_f): New proc. (test_objdump_h): Likewise. (test_objdump_t): Likewise. (test_objdump_r): Likewise. (test_objdump_s): Likewise. Add objdump tests on archive.
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-2/+5
This patch adds support for the new SPARC M8 processor (implementing OSA 2017) to binutils. New instructions: - Dictionary Unpack + dictunpack - Partitioned Compare with shifted result + Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl - Partitioned Dual-Equal compared, with shifted result + fpcmpde{8,16,32}shl - Partitioned Unsigned Range Compare, with shifted result + fpcmpur{8,16,32}shl - 64-bit shifts on Floating-Point registers + fps{ll,ra,rl}64x - Misaligned loads and stores + ldm{sh,uh,sw,uw,x,ux} + ldm{sh,uh,sw,uw,x,ux}a + ldmf{s,d} + ldmf{s,d}a + stm{h,w,x} + stm{h,w,x}a + stmf{s,d} + stmf{s,d}a - Oracle Numbers + on{add,sub,mul,div} - Reverse Bytes/Bits + revbitsb + revbytes{h,w,x} - Run-Length instructions + rle_burst + rle_length - New crypto instructions + sha3 - Instruction to read the new register %entropy + rd %entropy New Alternate Address Identifiers: - 0x24, #ASI_CORE_COMMIT_COUNT - 0x24, #ASI_CORE_SELECT_COUNT - 0x48, #ASI_ARF_ECC_REG - 0x53, #ASI_ITLB_PROBE - 0x58, #ASI_DSFAR - 0x5a, #ASI_DTLB_PROBE_PRIMARY - 0x5b, #ASI_DTLB_PROBE_REAL - 0x64, #ASI_CORE_SELECT_COMMIT_NHT The new assembler command-line options for selecting the M8 architecture are: -Av9m8 or -Asparc6 for 64-bit binaries. -Av8plusm8 for 32-bit (v8+) binaries. The corresponding disassembler command-line options are: -msparc:v9m8 for 64-bit binaries. -msparc:v8plusm8 for 32-bit (v8+) binaries. Tested for regressions in the following targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux bfd/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v9m8): Define. (bfd_mach_sparc_v8plusm8): Likewise. (bfd_mach_sparc_v9_p): Adjust to M8. (bfd_mach_sparc_64bit_p): Likewise. * aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and bfd_mach_sparc_v8plusm8. * bfd-in2.h: Regenerated. * cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and sparc:v8plusm8. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and SHA3. * elf32-sparc.c (elf32_sparc_final_write_processing): Handle bfd_mach_sparc_v8plusm8. binutils/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Mention the SPARC M8 support. gas/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6', `v9m8' and `v8plusm8'. (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8. (get_hwcap_name): Support the M8 hardware capabilities. (sparc_ip): Handle new operand types. * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and -Asparc6, and the corresponding -xarch aliases. * testsuite/gas/sparc/sparc6.s: New file. * testsuite/gas/sparc/sparc6.d: Likewise. * testsuite/gas/sparc/sparc6-diag.s: Likewise. * testsuite/gas/sparc/sparc6-diag.l: Likewise. * testsuite/gas/sparc/fpcmpshl.s: Likewise. * testsuite/gas/sparc/fpcmpshl.d: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise. * testsuite/gas/sparc/ldm-stm.s: Likewise. * testsuite/gas/sparc/ldm-stm.d: Likewise. * testsuite/gas/sparc/ldm-stm-diag.s: Likewise. * testsuite/gas/sparc/ldm-stm-diag.l: Likewise. * testsuite/gas/sparc/ldmf-stmf.s: Likewise. * testsuite/gas/sparc/ldmf-stmf.d: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise. * testsuite/gas/sparc/on.s: Likewise. * testsuite/gas/sparc/on.d: Likewise. * testsuite/gas/sparc/on-diag.s: Likewise. * testsuite/gas/sparc/on-diag.l: Likewise. * testsuite/gas/sparc/rle.s: Likewise. * testsuite/gas/sparc/rle.d: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests. * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY. * testsuite/gas/sparc/rdasr.d: Likewise. include/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define. (ELF_SPARC_HWCAP2_ONADDSUB): Likewise. (ELF_SPARC_HWCAP2_ONMUL): Likewise. (ELF_SPARC_HWCAP2_ONDIV): Likewise. (ELF_SPARC_HWCAP2_DICTUNP): Likewise. (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise. (ELF_SPARC_HWCAP2_RLE): Likewise. (ELF_SPARC_HWCAP2_SHA3): Likewise. * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8 and adjust SPARC_OPCODE_ARCH_MAX. (HWCAP2_SPARC6): Define. (HWCAP2_ONADDSUB): Likewise. (HWCAP2_ONMUL): Likewise. (HWCAP2_ONDIV): Likewise. (HWCAP2_DICTUNP): Likewise. (HWCAP2_FPCMPSHL): Likewise. (HWCAP2_RLE): Likewise. (HWCAP2_SHA3): Likewise. (OPM): Likewise. (OPMI): Likewise. (ONFCN): Likewise. (REVFCN): Likewise. (SIMM10): Likewise. opcodes/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. (X_IMM2): Define. (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8. (print_insn_sparc): Handle new operand types. * sparc-opc.c (MASK_M8): Define. (v6): Add MASK_M8. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Likewise. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (v9andleon): Likewise. (m8): Define. (HWS_VM8): Define. (HWS2_VM8): Likewise. (sparc_opcode_archs): Add entry for "m8". (sparc_opcodes): Add OSA2017 and M8 instructions dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, fpx{ll,ra,rl}64x, ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, ASI_CORE_SELECT_COMMIT_NHT.
2017-05-10bfd: new BFD target entry point _bfd_set_reloc.Jose E. Marchesi1-0/+5
This patch adds a new entry point to the BFD_JUMP_TABLE_RELOCS. The previous common implementation `bfd_set_reloc', in bfd/bfd.c, has been moved to bfd/reloc.c with the name `_bfd_generic_set_reloc', and all BFD targets has been adapted to use it. This patch doesn't introduce any change on functionality, but prepares the ground for further work. bfd/ChangeLog: 2017-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * targets.c (BFD_JUMP_TABLE_RELOCS): Add NAME##_set_reloc. (struct bfd_target): New field _bfd_set_reloc. * bfd.c (bfd_set_reloc): Call backend _set_bfd. * reloc.c (_bfd_generic_set_reloc): New function. * coffcode.h (coff_set_reloc): Define to _bfd_generic_set_reloc. * nlm-target.h (nlm_set_reloc): Likewise. * coff-rs6000.c (_bfd_xcoff_set_reloc): Likewise. * aout-tic30.c (MY_set_reloc): Likewise. * aout-target.h (MY_set_reloc): Likewise. * elfxx-target.h (bfd_elfNN_set_reloc): Likewise. * coff-alpha.c (_bfd_ecoff_set_reloc): Likewise. * mach-o-target.c (bfd_mach_o_set_reloc): Likewise. * vms-alpha.c (alpha_vms_set_reloc): Likewise. * aout-adobe.c (aout_32_set_reloc): Likewise. * bout.c (b_out_set_reloc): Likewise. * coff-mips.c (_bfd_ecoff_set_reloc): Likewise. * i386os9k.c (aout_32_set_reloc): Likewise. * ieee.c (ieee_set_reloc): Likewise. * oasys.c (oasys_set_reloc): Likewise. * som.c (som_set_reloc): Likewise. * versados.c (versados_set_reloc): Likewise. * coff64-rs6000.c (rs6000_xcoff64_vec): Add _bfd_generic_set_reloc. (rs6000_xcoff64_aix_vec): LIkewise. * libbfd.c (_bfd_norelocs_set_reloc): New function. * libbfd-in.h: Prototype for _bfd_norelocs_set_reloc. * i386msdos.c (msdos_set_reloc): Define to _bfd_norelocs_set_reloc. * elfcode.h (elf_set_reloc): Define. * bfd-in2.h: Regenerated.
2017-04-23PR 21414, null pointer deref of _bfd_elf_large_com_section symAlan Modra1-0/+12
PR 21414 * section.c (GLOBAL_SYM_INIT): Make available in bfd.h. * elf.c (lcomm_sym): New. (_bfd_elf_large_com_section): Use lcomm_sym section symbol. * bfd-in2.h: Regenerate.
2017-04-13Regen bfd-in2.hAlan Modra1-1/+2
* bfd-in2.h: Regenerate.
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ↵Pip Cet1-0/+12
gas and the binutils. binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate.
2017-03-27Add minimal support for WebAssembly backend to the BFD library.Pip Cet1-0/+2
include * elf/wasm32.h: New file to support wasm32 architecture. bfd * cpu-wasm32.c: New file to support wasm32 architecture. * elf32-wasm32.c: New file to support wasm32 architecture. * Makefile.am: Add wasm32 architecture. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise.
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and ↵Nick Clifton1-2/+2
R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12. PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-02-28PowerPC addpcis fixAlan Modra1-0/+1
This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range.
2017-02-17bfd: Rename warn_deprecatedPedro Alves1-5/+5
Give this bfd-internal symbol with external linkage a _bfd_ prefix to avoid collisions in the global symbol namespace. bfd/ChangeLog: 2017-02-17 Pedro Alves <palves@redhat.com> * bfd-in.h (bfd_read, bfd_write): Adjust to rename. (warn_deprecated): Rename to ... (_bfd_warn_deprecated): ... this. * libbfd.c (warn_deprecated): Rename to ... (_bfd_warn_deprecated): ... this. * bfd-in2.h: Regenerate.
2017-02-16[Patch] Add BFD_LINKER_CREATED to BFD_FLAGS_SAVEDJiong Wang1-2/+3
bfd/ * bfd.c (BFD_FLAGS_SAVED): Add BFD_LINKER_CREATED. * bfd-in2.h: Regenerated. Bug exposed by https://sourceware.org/ml/binutils/2017-02/msg00128.html
2017-01-12Add support for locating separate debug info files via the build-id method.Nick Clifton1-0/+2
PR binutils/20876 bfd * opncls.c (find_separate_debug_file): Add include_dirs parameter. Only include the directory part of the bfd's filename in search paths if include_dirs is true. Add a couple of extra locations for looking for debug files. ( bfd_follow_gnu_debuglink): Update invocation of find_separate_debug_file. (bfd_follow_gnu_debugaltlink): Likewise. (get_build_id): New function: Finds the build-id of the given bfd. (get_build_id_name): New function: Computes the name of the separate debug info file for a bfd, based upon its build-id. (check_build_id_file): New function: Checks to see if a separate debug info file exists at the given location, and that its build-id matches that of the original bfd. (bfd_follow_build_id_debuglink): New function: Finds a separate debug info file for a given bfd by using the build-id method. * dwarf2.c (_bfd_dwarf2_slurp_debug_info): Try using the build-id method of locating a separate debug info file before using the debuglink method. * bfd-in2.h: Regenerate. binutils * NEWS: Mention the new feature. * testsuite/binutils-all/objdump.exp (test_build_id_debuglink): New proc to test the location of separate debug info files using the build-id method.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-31PRU BFD supportDimitar Dimitrov1-0/+37
include/ * elf/common.h: Add PRU ELF. * elf/pru.h: New file. * opcode/pru.h: New file. * dis-asm.h (print_insn_pru): Declare. bfd/ * archures.c: Add bfd_arch_pru. * Makefile.am: Add PRU target. * config.bfd: Ditto. * configure.ac: Ditto. * elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA. * targets.c: Add pru_elf32_vec. * reloc.c: Add PRU relocations. * cpu-pru.c: New file. * elf32-pru.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. * bfd-in2.h: Regenerate * libbfd.h: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-20Rework RISC-V relocationsAndrew Waterman1-0/+9
Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki1-0/+4
Respect any ASE flags recorded in ELF file structures for the purpose of selecting instructions to be disassembled, preventing code from being hex-dumped even though having been clearly indicated as valid at the assembly time. Use date from the MIPS ABI flags structure if present, and otherwise there may be an MDMX ASE flag set in the ELF file header. For backwards compatibility only set extra flags and do not clear any, preserving all previously set by the architecture selected to be disassembled for. include/ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct typedef as `elf_internal_abiflags_v0'. bfd/ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration. (bfd_mips_elf_get_abiflags): New prototype. * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (mips_convert_abiflags_ases): New function. (set_default_mips_dis_options): Also infer ASE flags from ELF file structures. binutils/ * testsuite/binutils-all/mips/mips-ase-1.d: New test. * testsuite/binutils-all/mips/mips-ase-2.d: New test. * testsuite/binutils-all/mips/mips-ase-3.d: New test. * testsuite/binutils-all/mips/mips-ase-1.s: New test source. * testsuite/binutils-all/mips/mips-ase-2.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+43
bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
2016-10-12BFD_FAKE_SECTION macro paramsAlan Modra1-2/+2
Order NAME, IDX, FLAGS as per STD_SECTION macro. * section.c (BFD_FAKE_SECTION): Reorder parameters. Formatting. (STD_SECTION): Adjust to suit. * elf.c (_bfd_elf_large_com_section): Likewise. * bfd-in2.h: Regenerate.
2016-10-07Pass link_info to _bfd_merge_private_bfd_dataAlan Modra1-5/+6
Most BFD linker functions take a bfd_link_info param, which reinforces the fact that they are linker functions and allow access to linker callbacks, eg. einfo for printing errors. I was going to use einfo for --fatal-warnings support before I decided a better way was the patch commit 4519d071. bfd/ * targets.c (bfd_target <_bfd_merge_private_bfd_data>): Replace obfd param with struct bfd_link_info param. Update all callers. * linker.c (bfd_merge_private_bfd_data): Likewise. (_bfd_generic_verify_endian_match): Likewise. * aoutf1.h (sunos_merge_private_bfd_data): Likewise. * coff-arm.c (coff_arm_merge_private_bfd_data): Likewise. * elf-attrs.c (_bfd_elf_merge_object_attributes): Likewise. * elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Likewise. (_bfd_elf_merge_object_attributes): Likewise. * elf-m10300.c (_bfd_mn10300_elf_merge_private_bfd_data): Likewise. * elf-s390-common.c (elf_s390_merge_obj_attributes): Likewise. * elf32-arc.c (arc_elf_merge_private_bfd_data): Likewise. * elf32-arm.c (elf32_arm_merge_eabi_attributes): Likewise. (elf32_arm_merge_private_bfd_data): Likewise. * elf32-bfin.c (elf32_bfin_merge_private_bfd_data): Likewise. * elf32-cr16.c (_bfd_cr16_elf_merge_private_bfd_data): Likewise. * elf32-cris.c (cris_elf_merge_private_bfd_data): Likewise. * elf32-frv.c (frv_elf_merge_private_bfd_data): Likewise. * elf32-h8300.c (elf32_h8_merge_private_bfd_data): Likewise. * elf32-i370.c (i370_elf_merge_private_bfd_data): Likewise. * elf32-iq2000.c (iq2000_elf_merge_private_bfd_data): Likewise. * elf32-m32c.c (m32c_elf_merge_private_bfd_data): Likewise. * elf32-m32r.c (m32r_elf_merge_private_bfd_data): Likewise. * elf32-m68hc1x.c (_bfd_m68hc11_elf_merge_private_bfd_data): Likewise. * elf32-m68hc1x.h (_bfd_m68hc11_elf_merge_private_bfd_data): Likewise. * elf32-m68k.c (elf32_m68k_merge_private_bfd_data): Likewise. * elf32-mcore.c (mcore_elf_merge_private_bfd_data): Likewise. * elf32-mep.c (mep_elf_merge_private_bfd_data): Likewise. * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Likewise. (elf32_msp430_merge_private_bfd_data): Likewise. * elf32-mt.c (mt_elf_merge_private_bfd_data): Likewise. * elf32-nds32.c (nds32_elf_merge_private_bfd_data): Likewise. * elf32-nios2.c (nios2_elf32_merge_private_bfd_data): Likewise. * elf32-or1k.c (elf32_or1k_merge_private_bfd_data): Likewise. * elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): Likewise. (ppc_elf_merge_obj_attributes): Likewise. (ppc_elf_merge_private_bfd_data): Likewise. * elf32-rl78.c (rl78_elf_merge_private_bfd_data): Likewise. * elf32-rx.c (rx_elf_merge_private_bfd_data): Likewise. * elf32-s390.c (elf32_s390_merge_private_bfd_data): Likewise. * elf32-score.c (s3_elf32_score_merge_private_bfd_data): Likewise. (elf32_score_merge_private_bfd_data): Likewise. * elf32-score.h (s7_elf32_score_merge_private_bfd_data): Likewise. * elf32-score7.c (s7_elf32_score_merge_private_bfd_data): Likewise. * elf32-sh.c (sh_merge_bfd_arch, sh_elf_merge_private_data): Likewise. * elf32-sh64.c (sh64_elf_merge_private_data): Likewise. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Likewise. * elf32-tic6x.c (elf32_tic6x_merge_attributes): Likewise. (elf32_tic6x_merge_private_bfd_data): Likewise. * elf32-v850.c (v850_elf_merge_private_bfd_data): Likewise. * elf32-vax.c (elf32_vax_merge_private_bfd_data): Likewise. * elf32-visium.c (visium_elf_merge_private_bfd_data): Likewise. * elf32-xtensa.c (elf_xtensa_merge_private_bfd_data): Likewise. * elf64-ia64-vms.c (elf64_ia64_merge_private_bfd_data): Likewise. * elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Likewise. * elf64-s390.c (elf64_s390_merge_private_bfd_data): Likewise. * elf64-sh64.c (sh_elf64_merge_private_data): Likewise. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. * elfnn-aarch64.c (elfNN_aarch64_merge_private_bfd_data): Likewise. * elfnn-ia64.c (elfNN_ia64_merge_private_bfd_data): Likewise. * elfxx-mips.c (mips_elf_merge_obj_e_flags): Likewise. (mips_elf_merge_obj_attributes): Likewise. (_bfd_mips_elf_merge_private_bfd_data): Likewise. * elfxx-mips.h (_bfd_mips_elf_merge_private_bfd_data): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): Likewise. * elfxx-sparc.h (_bfd_sparc_elf_merge_private_bfd_data): Likewise. * elfxx-target.h (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. * elfxx-tilegx.c (_bfd_tilegx_elf_merge_private_bfd_data): Likewise. * elfxx-tilegx.h (_bfd_tilegx_elf_merge_private_bfd_data): Likewise. * libbfd-in.h (_bfd_generic_bfd_merge_private_bfd_data): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld/ * ldlang.c (lang_check): Update bfd_merge_private_bfd_data call.
2016-10-07bfd_merge_private_bfd_data tidyAlan Modra1-5/+5
bfd_merge_private_bfd_data and _bfd_generic_verify_endian_match are linker functions, so move them to linker.c. bfd/ * Makefile.am (LIBBFD_H_FILES): Update. * doc/Makefile.am (LIBBFD_H_DEP): Likewise. * cpu-sh.c (sh_merge_bfd_arch): Move to.. * elf32-sh.c: ..here, and make static. * elf32-arc.c (arc_elf_merge_private_bfd_data): Delete extraneous error. * elf32-cris.c (cris_elf_merge_private_bfd_data): Don't call _bfd_generic_verify_endian_match. * elf32-microblaze.c (microblaze_elf_merge_private_bfd_data): Delete. (bfd_elf32_bfd_merge_private_bfd_data): Define as _bfd_generic_verify_endian_match. * elf32-mt.c (mt_elf_merge_private_bfd_data): Don't test boolean == FALSE. * elf32-xgate.c (_bfd_xgate_elf_merge_private_bfd_data): Delete. (bfd_elf32_bfd_merge_private_bfd_data): Don't define. * elf32-xgate.h (_bfd_xgate_elf_merge_private_bfd_data): Delete. * libbfd-in.h (_bfd_generic_verify_endian_match): Delete. * libbfd.c (_bfd_generic_verify_endian_match): Move to.. * linker.c: ..here, and make internal. * bfd.c (bfd_merge_private_bfd_data): Move to.. * linker.c: ..here. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. opcodes/ * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
2016-09-30Make bfd_error_handler_type like vprintfAlan Modra1-5/+2
It was like printf, which means you can't use bfd_set_error_handler to hook in a function to do something and then call the original handler. The patch also deletes some unused functions and makes pointers local. bfd/ * bfd-in.h: Include stdarg.h. * bfd.c (bfd_error_handler_type): Make like vprintf. (_bfd_error_internal): Rename from _bfd_error_handler. Make static. (error_handler_internal): New function, split out from.. (_bfd_default_error_handler): ..here. Rename to _bfd_error_handler. (bfd_set_error_handler): Update. (bfd_get_error_handler, bfd_get_assert_handler): Delete. (_bfd_assert_handler): Make static. * coffgen.c (null_error_handler): Update params. * elf-bfd.h (struct elf_backend_data <link_order_error_handler>): Don't use bfd_error_handler_type. * elf64-mmix.c (mmix_dump_bpo_gregs): Likewise. * elfxx-target.h (elf_backend_link_order_error_handler): Default to _bfd_error_handler. * libbfd-in.h (_bfd_default_error_handler): Don't declare. (bfd_assert_handler_type): Likewise. (_bfd_error_handler): Update. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld/ * ldlang.c (ignore_bfd_errors): Update params.
2016-08-26Reduce parameter list in bfd_elf32_arm_target_relocsThomas Preud'homme1-3/+21
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * bfd-in.h (struct elf32_arm_params): Define. (bfd_elf32_arm_set_target_relocs): Rename into ... (bfd_elf32_arm_set_target_params): This. Use a struct elf32_arm_params to pass all parameters but the bfd and bfd_link_info. * bfd-in2.h: Regenerate. * elf32-arm.c (bfd_elf32_arm_set_target_relocs): Rename into ... (bfd_elf32_arm_set_target_params): This. Pass all values via a struct elf32_arm_params rather than as individual parameters. ld/ * emultempl/armelf.em (params): New static variable. (thumb_entry_symbol, byteswap_code, target1_is_rel, target2_type, fix_v4bx, use_blx, vfp11_denorm_fix, stm32l4xx_fix, fix_cortex_a8, no_enum_size_warning, no_wchar_size_warning, pic_veneer, merge_exidx_entries, fix_arm1176, cmse_implib): move as part of the above new structure. (arm_elf_before_allocation): Access static variable from the params structure. (gld${EMULATION_NAME}_finish): Likewise. (arm_elf_create_output_section_statements): Likewise and pass the address of that structure to bfd_elf32_arm_set_target_relocs instead of the static variables. (PARSE_AND_LIST_ARGS_CASES): Access static variable from the params structure.
2016-08-26Fixes to legacy ARC relocations.Cupertino Miranda1-3/+4
Added support for ARC_SDA_12 reloc. Fixed ARC_N32_ME. Added ME (middle-endian) to ARC_SDA_12 reloc. bfd/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12 relocation. * bfd-in2.h: Regenerated from the previous changes. * libbfd.h: Regenerated from the previous changes. include/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12, SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations. * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation.
2016-08-26Add support for stable secure gateway veneers addressesThomas Preud'homme1-1/+1
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * bfd-in.h (bfd_elf32_arm_set_target_relocs): Add a new parameter for the input import library bfd. * bfd-in2.h: Regenerate. * elf32-arm.c (struct elf32_arm_link_hash_table): New in_implib_bfd and new_cmse_stub_offset fields. (stub_hash_newfunc): Initialize stub_offset and stub_template_size to -1. (elf32_arm_add_stub): Likewise for stub_offset. (arm_new_stubs_start_offset_ptr): New function. (arm_build_one_stub): Only allocate a stub_offset if it is -1. Allow empty SG veneers to have zero relocations. (arm_size_one_stub): Only initialize stub size and template information for non empty veneers. Do not update veneer section size if veneer already has an offset. (elf32_arm_create_stub): Return the stub entry pointer or NULL instead of a boolean indicating success or failure. (cmse_scan): Change stub_changed parameter into an integer pointer parameter cmse_stub_created to count the number of stub created and adapt to change of return value in elf32_arm_create_stub. (cmse_entry_fct_p): New function. (arm_list_new_cmse_stub): Likewise. (set_cmse_veneer_addr_from_implib): Likewise. (elf32_arm_size_stubs): Define cmse_stub_created, pass its address to cmse_scan instead of that of cmse_stub_changed to compute the number of stub created and use it to initialize stub_changed. Call set_cmse_veneer_addr_from_implib after all cmse_scan. Adapt to change of return value in elf32_arm_create_stub. Use arm_stub_section_start_offset () if not NULL to initialize size of secure gateway veneers section. Initialize stub_offset of Cortex-A8 erratum fix to -1. Use ret to hold return value. (elf32_arm_build_stubs): Use arm_stub_section_start_offset () if not NULL to initialize size of secure gateway veneers section. Adapt comment to stress the importance of zeroing veneer section content. (bfd_elf32_arm_set_target_relocs): Add new in_implib_bfd parameter to initialize eponymous field in struct elf32_arm_link_hash_table. ld/ * emultempl/armelf.em (in_implib_filename): Declare and initialize new variable. (arm_elf_create_output_section_statements): Open import input library file for writing and pass resulting in_implib_bfd to bfd_elf32_arm_set_target_relocs. (PARSE_AND_LIST_PROLOGUE): Define OPTION_IN_IMPLIB option. (PARSE_AND_LIST_LONGOPTS): Define --in-implib option. (PARSE_AND_LIST_OPTIONS): Add help message for --in-implib option. (PARSE_AND_LIST_ARGS_CASES): Handle new OPTION_IN_IMPLIB case. * ld.texinfo (--cmse-implib): Update to mention --in-implib. (--in-implib): Document new option. * NEWS: Likewise. * testsuite/ld-arm/arm-elf.exp (Secure gateway import library generation): add --defsym VER=1 to gas CLI. (Secure gateway import library generation: errors): Likewise. (Input secure gateway import library): New test. (Input secure gateway import library: no output import library): Likewise. (Input secure gateway import library: not an SG input import library): Likewise. (Input secure gateway import library: earlier stub section base): Likewise. (Input secure gateway import library: later stub section base): Likewise. (Input secure gateway import library: veneer comeback): Likewise. (Input secure gateway import library: entry function change): Likewise. * testsuite/ld-arm/cmse-implib.s: Add input import library testing. * testsuite/ld-arm/cmse-implib.rd: Update accordingly. * testsuite/ld-arm/cmse-new-implib.out: New file. * testsuite/ld-arm/cmse-new-implib.rd: Likewise. * testsuite/ld-arm/cmse-new-implib-no-output.out: Likewise. * testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out: Likewise. * testsuite/ld-arm/cmse-new-earlier-later-implib.out: Likewise. * testsuite/ld-arm/cmse-new-comeback-implib.rd: Likewise. * testsuite/ld-arm/cmse-new-wrong-implib.out: Likewise.
2016-08-042016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>Thomas Preud'homme1-1/+1
bfd/ * bfd-in.h (bfd_elf32_arm_set_target_relocs): Add one parameter. * bfd-in2.h: Regenerate. * elf32-arm.c (struct elf32_arm_link_hash_table): Declare new cmse_implib field. (bfd_elf32_arm_set_target_relocs): Add new parameter to initialize cmse_implib field in struct elf32_arm_link_hash_table. (elf32_arm_filter_cmse_symbols): New function. (elf32_arm_filter_implib_symbols): Likewise. (elf_backend_filter_implib_symbols): Define to elf32_arm_filter_implib_symbols. ld/ * emultempl/armelf.em (cmse_implib): Declare and define this new static variable. (arm_elf_create_output_section_statements): Add new cmse_implib parameter. (OPTION_CMSE_IMPLIB): Define macro. (PARSE_AND_LIST_LONGOPTS): Add entry for new --cmse-implib switch. (PARSE_AND_LIST_OPTIONS): Likewise. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_CMSE_IMPLIB case. * ld.texinfo (--cmse-implib): Document new option. * testsuite/ld-arm/arm-elf.exp (Secure gateway import library generation): New test. (Secure gateway import library generation: errors): Likewise. * testsuite/ld-arm/cmse-implib.s: New file. * testsuite/ld-arm/cmse-implib-errors.out: Likewise. * testsuite/ld-arm/cmse-implib.rd: Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 4Alan Modra1-3/+3
Not much to see here, just renaming a function. bfd/ * targets.c (bfd_seach_for_target): Rename to.. (bfd_iterate_over_targets): ..this. Rewrite doc. * bfd-in2.h: Regenerate. ld/ * ldlang.c (open_output): Replace bfd_search_for_target with bfd_iterate_over_targets. Localize vars.
2016-07-16Don't include libbfd.h outside of bfd, part 2Alan Modra1-0/+3
Make bfd_default_set_arch_mach available to a bunch of gas backend files. bfd/ * archures.c (bfd_default_set_arch_mach): Make available in bfd.h. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-epiphany.c: Don't include libbfd.h. * config/tc-frv.c: Likewise. * config/tc-ip2k.c: Likewise. * config/tc-iq2000.c: Likewise. * config/tc-m32c.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mt.c: Likewise. * config/tc-nios2.c: Likewise.
2016-07-16Don't include libbfd.h outside of bfd, part 1Alan Modra1-2/+10
Make BFD_ALIGN available to objcopy. Fix assertions. Don't use bfd_log2 in ppc32elf.em or bfd_malloc in xtensaelf.em and bucomm.c. bfd/ * libbfd-in.h (BFD_ALIGN): Move to.. * bfd-in.h: ..here. * elf32-ppc.h (struct ppc_elf_params): Add pagesize. * elf32-ppc.c (default_params): Adjust init. (ppc_elf_link_params): Set pagesize_p2. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. binutils/ * ar.c: Don't include libbfd.h. * objcopy.c: Likewise. * bucomm.c (bfd_get_archive_filename): Use xmalloc rather than bfd_malloc. gas/ * config/bfin-parse.y: Don't include libbfd.h. * config/tc-bfin.c: Likewise. * config/tc-rl78.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-metag.c: Likewise. (create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT. * Makefile.am: Update dependencies. * Makefile.in: Regenerate. ld/ * ldlang.c: Don't include libbfd.h. * emultempl/nds32elf.em: Likewise. * emultempl/ppc64elf.em: Likewise. * emultempl/ppc32elf.em: Likewise. (pagesize): Delete. (params): Update init. (ppc_after_open_output): Use params.pagesize. Don't call bfd_log2. (PARSE_AND_LIST_ARGS_CASES): Use params.pagesize. * emultempl/sh64elf.em: Don't include libbfd.h. (after_allocation): Use ASSERT, not BFD_ASSERT. * emultempl/xtensaelf.em: Don't include libbfd.h. (replace_insn_sec_with_prop_sec): Use xmalloc, not bfd_malloc. * Makefile.am: Update dependencies. * Makefile.in: Regenerate.
2016-07-05[ARM] Change noread to purecode.Andre Vieria1-2/+2
bfd/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * bfd-in2.h (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. (elf32_arm_fake_sections): Likewise. (elf_32_arm_section_flags): Likewise. (elf_32_arm_lookup_section_flags): Likewise. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. binutils/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE. (process_section_headers): Rename noread to purecode. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. include/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * elf/arm.h (SHF_ARM_NOREAD): Rename to ... (SHF_ARM_PURECODE): ... this. ld/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm_noread.ld: Renamed to ... testsuite/ld-arm/arm_purecode.ld: ... this, and replaced all noread's by purecode.
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki1-0/+3
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1' and the usual MIPS16 bit shuffling applies to relocated field handling, as per the encoding of the branch target in the extended form of the MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions. include/ * elf/mips.h (R_MIPS16_PC16_S1): New relocation. bfd/ * elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_PC16_S1. (mips16_reloc_map): Likewise. * elf64-mips.c (mips16_elf64_howto_table_rel): Likewise. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfn32-mips.c (elf_mips16_howto_table_rel): Likewise. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfxx-mips.c (mips16_branch_reloc_p): New function. (mips16_reloc_p): Handle R_MIPS16_PC16_S1. (b_reloc_p): Likewise. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_check_relocs): Likewise. * reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-mips.c (mips16_reloc_p): Handle BFD_RELOC_MIPS16_16_PCREL_S1. (b_reloc_p): Likewise. (limited_pcrel_reloc_p): Likewise. (md_pcrel_from): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. (md_convert_frag): Likewise. (mips_fix_adjustable): Update comment. * testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-3.l: Remove file. * testsuite/gas/mips/mips16-branch-absolute.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.s: Add padding. * testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid implicit instruction padding, avoid MIPS16 JR->JRC conversion. * testsuite/gas/mips/branch-weak-6.d: New test. * testsuite/gas/mips/branch-weak-7.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-3.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test. * testsuite/ld-mips-elf/mips16-branch.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-1/+0
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-18Rename bfd_plugin_uknown to bfd_plugin_unknownH.J. Lu1-1/+1
bfd/ * bfd.c (bfd_plugin_format): Rename bfd_plugin_uknown to bfd_plugin_unknown. * bfd-in2.h: Regenerated. * plugin.c (bfd_plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown. ld/ * plugin.c (plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown.
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine ↵Jose E. Marchesi1-2/+18
numbers. This patch adds support for the opcode architectures SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}. Note that for arches up to v9b (UltraSPARC III), the detection of the BFD machine type was based on the bits in the e_machine field of the ELF header. However, there are no more available bits in that field, so this patch takes the approach of using the hardware capabilities stored in the object attributes HWCAPS/HWCAPS2 in order to characterize the machine the object was built for. bfd/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v8plusc): Define. (bfd_mach_sparc_v9c): Likewise. (bfd_mach_sparc_v8plusd): Likewise. (bfd_mach_sparc_v9d): Likewise. (bfd_mach_sparc_v8pluse): Likewise. (bfd_mach_sparc_v9e): Likewise. (bfd_mach_sparc_v8plusv): Likewise (bfd_mach_sparc_v9v): Likewise. (bfd_mach_sparc_v8plusm): Likewise. (bfd_mach_sparc_v9m): Likewise. (bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m. (bfd_mach_sparc_64bit_p): Likewise. * bfd-in2.h: Regenerate. * cpu-sparc.c (arch_info_struct): Add entries for bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * elf32-sparc.c (elf32_sparc_final_write_processing): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise. include/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D, SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and SPARC_OPCODE_ARCH_V9M. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * sparc-opc.c (MASK_V9C): Define. (MASK_V9D): Likewise. (MASK_V9E): Likewise. (MASK_V9V): Likewise. (MASK_V9M): Likewise. (v6): Add MASK_V9{C,D,E,V,M}. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9andleon): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Define. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-14Delete bfd_my_archive macroAlan Modra1-1/+0
Many more places use abfd->my_archive rather than bfd_my_archive (abfd), so let's make the code consistently use the first idiom. bfd/ * bfd-in.h (bfd_my_archive): Delete. * bfd-in2.h: Regenerate. binutils/ * ar.c: Expand uses of bfd_my_archive. * size.c: Likewise. ld/ * ldlang.c: Expand uses of bfd_my_archive. * ldmain.c: Likewise. * ldmisc.c: Likewise. * plugin.c: Likewise.
2016-06-07PowerPC VLEAlan Modra1-7/+0
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-05-23Enable R_AARCH64_NONE for 64-bit code.Jim Wilson1-0/+3
* elfnn-aarch64.c: Unconditionally enable R_AARCH64_NULL and R_AARCH64_NONE. Use HOWTO64 for R_AARCH64_NULL. * relocs.c: Add BFD_RELOC_AARCH64_NULL. * bfd-in2.h: Regenerate. * libbfd.h: Likewise.
2016-05-23Support for dedicated output section for some ARM veneer typesThomas Preud'homme1-0/+3
2016-05-23 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * bfd-in.h (bfd_elf32_arm_keep_private_stub_output_sections): Declare bfd hook. * bfd-in2.h: Regenerate. * elf32-arm.c (arm_dedicated_stub_output_section_required): New function. (arm_dedicated_stub_output_section_required_alignment): Likewise. (arm_dedicated_stub_output_section_name): Likewise. (arm_dedicated_stub_input_section_ptr): Likewise. (elf32_arm_create_or_find_stub_sec): Add stub type parameter and function description comment. Add support for dedicated output stub section to given stub types. (elf32_arm_add_stub): Add a stub type parameter and pass it down to elf32_arm_create_or_find_stub_sec. (elf32_arm_create_stub): Pass stub type down to elf32_arm_add_stub. (elf32_arm_size_stubs): Pass stub type when calling elf32_arm_create_or_find_stub_sec for Cortex-A8 erratum veneers. (bfd_elf32_arm_keep_private_stub_output_sections): New function. ld/ * emultempl/armelf.em (arm_elf_before_allocation): Call bfd_elf32_arm_keep_private_stub_output_sections before generic before_allocation function.
2016-05-10Allow stubs without associated input section in ARM backendThomas Preud'homme1-1/+2
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * bfd-in.h (elf32_arm_size_stubs): Add an output section parameter. * bfd-in2.h: Regenerated. * elf32-arm.c (struct elf32_arm_link_hash_table): Add an output section parameter to add_stub_section callback. (elf32_arm_create_or_find_stub_sec): Get output section from link_sec and pass it down to add_stub_section. (elf32_arm_add_stub): Set section to stub_sec if NULL before using it for error message. (elf32_arm_size_stubs): Add output section parameter to add_stub_section function pointer parameter. ld/ * emultempl/armelf.em (elf32_arm_add_stub_section): Add output_section parameter and rename input_section parameter to after_input_section. Append input stub section to the output section if after_input_section is NULL.
2016-05-03[AArch64] Also puts value in place for R_AARCH64_RELATIVEJiong Wang1-2/+2
When handling absolute relocations for global symbols bind within the shared object, AArch64 will generate one dynamic RELATIVE relocation, but won't apply the value for this absolution relocations at static linking stage. This is different from AArch64 gold linker and x86-64. This is not a bug as AArch64 is RELA, there is only guarantee that relocation addend is placed in the relocation entry. But some system softwares originally writen for x86-64 might assume AArch64 bfd linker gets the same behavior as x86-64, then they could take advantage of this buy skipping those RELATIVE dynamic relocations if the load address is the same as the static linking address. This patch makes AArch64 BFD linker applies absolution relocations at static linking stage for scenario described above. Meanwhile old AArch64 android loader has a bug (PR19163) which relies on current linker behavior as a workaround, so the same option --no-apply-dynamic-relocs added.
2016-04-21Add support for non-ELF targets to check their relocs.Nick Clifton1-0/+10
bfd * aout-adobe.c: Use _bfd_generic_link_check_relocs. * aout-target.h: Likewise. * aout-tic30.c: Likewise. * binary.c: Likewise. * bout.c: Likewise. * coff-alpha.c: Likewise. * coff-rs6000.c: Likewise. * coff64-rs6000.c: Likewise. * coffcode.h: Likewise. * i386msdos.c: Likewise. * i386os9k.c: Likewise. * ieee.c: Likewise. * ihex.c: Likewise. * libbfd-in.h: Likewise. * libecoff.h: Likewise. * mach-o-target.c: Likewise. * mmo.c: Likewise. * nlm-target.h: Likewise. * oasys.c: Likewise. * pef.c: Likewise. * plugin.c: Likewise. * ppcboot.c: Likewise. * som.c: Likewise. * srec.c: Likewise. * tekhex.c: Likewise. * versados.c: Likewise. * vms-alpha.c: Likewise. * xsym.c: Likewise. * elfxx-target.h: Use _bfd_elf_link_check_relocs. * linker.c (bfd_link_check_relocs): New function. (_bfd_generic_link_check_relocs): New function. * targets.c (BFD_JUMP_TABLE_LINK): Add initialization of _bfd_link_check_relocs field. (struct bfd_target)L Add _bfd_link_check_relocs field. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld * ldlang.c (lang_check_relocs): Use bfd_link_check_relocs in prefernce to _bfd_elf_link_check_relocs. Drop test for ELF targets. Do not stop the checks when problems are encountered. include * bfdlink.h: Add prototype for bfd_link_check_relocs.
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess1-0/+1
Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess1-0/+1
This commit introduces the nps400 machine type as a variant of arc. There's a new flag in the assembler to select this machine type. All other changes are just adding handling of the new machine type into the relevant places. The nps400 is an arc700 variant with some vendor specific instructions added into the instruction set. This commit does not add any of the new instructions, this is just laying the groundwork for future commits. However, in preparation for these new instructions a new opcode define for nps400 has been added to include/opcode/arc.h, this new opcode define is used in the assembler and disassembler along with the existing define for arc700 such that when assembling and disassembling for nps400 the user will have access to all arc700 instructions and all the nps400 vendor extension instructions. bfd/ChangeLog: * archures.c (bfd_mach_arc_nps400): Define. * bfd-in2.h: Regenerate. * cpu-arc.c (arch_info_struct): New entry for nps400, renumber some existing entries to make space. * elf32-arc.c (arc_elf_object_p): Add nps400 case. (arc_elf_final_write_processing): Likewise. binutils/ChangeLog: * readelf.c (decode_ARC_machine_flags): Handle nps400. gas/ChangeLog: * config/tc-arc.c (cpu_types): Add nps400 entry. (check_zol): Handle nps400. include/ChangeLog: * elf/arc.h (E_ARC_MACH_NPS400): Define. * opcode/arc.h (ARC_OPCODE_NPS400): Define. opcodes/ChangeLog: * arc-dis.c (print_insn_arc): Handle nps400.
2016-03-14Regenerate bfd-in2.hH.J. Lu1-1/+1
* bfd-in2.h: Regenerated.
2016-02-26Properly implement STT_COMMONH.J. Lu1-4/+13
The BFD configure option, --enable-elf-stt-common, can't be to used to verify STT_COMMON implementation with the normal binutils build. Instead, this patch removes it from BFD. It adds --elf-stt-common=[no|yes] to ELF assembler/objcopy and adds -z common/-z nocommon to ld. A configure option, --enable-elf-stt-common, is added to gas to specify whether ELF assembler should generate common symbols with the STT_COMMON type by default. Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF common symbols. bfd/ PR ld/19645 * bfd.c (bfd): Change flags to 20 bits. (BFD_CONVERT_ELF_COMMON): New. (BFD_USE_ELF_STT_COMMON): Likewise. (BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. * configure.ac: Remove --enable-elf-stt-common. * elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. * elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for STT_COMMON. * elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check STT_COMMON. (elf_link_convert_common_type): New function. (elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. Set sym.st_info after sym.st_shndx. * elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON to object_flags. (TARGET_LITTLE_SYM): Likewise. * syms.c (BSF_KEEP_G): Renamed to ... (BSF_ELF_COMMON): This. * bfd-in2.h: Regenerated. * config.in: Likewise. * configure: Likewise. binutils/ PR ld/19645 * NEWS: Mention --elf-stt-common= for objcopy. * doc/binutils.texi: Document --elf-stt-common= for objcopy. * objcopy.c (do_elf_stt_common): New. (command_line_switch): Add OPTION_ELF_STT_COMMON. (copy_options): Add --elf-stt-common=. (copy_usage): Add --elf-stt-common=. (copy_object): Also check do_elf_stt_common for ELF targets. (copy_file): Handle do_elf_stt_common. (copy_main): Handle OPTION_ELF_STT_COMMON. * readelf.c (apply_relocations): Support STT_COMMON. * testsuite/binutils-all/common-1.s: New file. * testsuite/binutils-all/common-1a.d: Likewise. * testsuite/binutils-all/common-1b.d: Likewise. * testsuite/binutils-all/common-1c.d: Likewise. * testsuite/binutils-all/common-1d.d: Likewise. * testsuite/binutils-all/common-1e.d: Likewise. * testsuite/binutils-all/common-1f.d: Likewise. * testsuite/binutils-all/common-2.s: Likewise. * testsuite/binutils-all/common-2a.d: Likewise. * testsuite/binutils-all/common-2b.d: Likewise. * testsuite/binutils-all/common-2c.d: Likewise. * testsuite/binutils-all/common-2d.d: Likewise. * testsuite/binutils-all/common-2e.d: Likewise. * testsuite/binutils-all/common-2f.d: Likewise. * testsuite/binutils-all/objcopy.exp (objcopy_test_elf_common_symbols): New proc. Run objcopy_test_elf_common_symbols for ELF targets gas/ PR ld/19645 * NEWS: Mention --enable-elf-stt-common and --elf-stt-common= for ELF assemblers. * as.c (flag_use_elf_stt_common): New. (show_usage): Add --elf-stt-common=. (option_values): Add OPTION_ELF_STT_COMMON. (std_longopts): Add --elf-stt-common=. (parse_args): Handle --elf-stt-common=. * as.h (flag_use_elf_stt_common): New. * config.in: Regenerated. * configure: Likewise. * configure.ac: Add --enable-elf-stt-common and define DEFAULT_GENERATE_ELF_STT_COMMON. * gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set. * doc/as.texinfo: Document --elf-stt-common=. * testsuite/gas/elf/common3.s: New file. * testsuite/gas/elf/common3a.d: Likewise. * testsuite/gas/elf/common3b.d: Likewise. * testsuite/gas/elf/common4.s: Likewise. * testsuite/gas/elf/common4a.d: Likewise. * testsuite/gas/elf/common4b.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. * testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a and common4b. * testsuite/gas/i386/dw2-compress-3.d: Renamed to ... * testsuite/gas/i386/dw2-compress-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/dw2-compressed-3.d: Renamed to ... * testsuite/gas/i386/dw2-compressed-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/i386.exp: Run dw2-compress-3a, dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead of dw2-compress-3 and dw2-compressed-3. include/ PR ld/19645 * bfdlink.h (bfd_link_elf_stt_common): New enum. (bfd_link_info): Add elf_stt_common. ld/ PR ld/19645 * NEWS: Mention -z common/-z nocommon for ELF targets. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle -z common and -z nocommon. * ld.texinfo: Document -z common/-z nocommon. * lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon. * testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and --elf-stt-common=yes with assembler. * testsuite/ld-elfcomm/common-1.s: New file. * testsuite/ld-elfcomm/common-1a.d: Likewise. * testsuite/ld-elfcomm/common-1b.d: Likewise. * testsuite/ld-elfcomm/common-1c.d: Likewise. * testsuite/ld-elfcomm/common-1d.d: Likewise. * testsuite/ld-elfcomm/common-1e.d: Likewise. * testsuite/ld-elfcomm/common-1f.d: Likewise. * testsuite/ld-elfcomm/common-2.s: Likewise. * testsuite/ld-elfcomm/common-2a.d: Likewise. * testsuite/ld-elfcomm/common-2b.d: Likewise. * testsuite/ld-elfcomm/common-2c.d: Likewise. * testsuite/ld-elfcomm/common-2d.d: Likewise. * testsuite/ld-elfcomm/common-2e.d: Likewise. * testsuite/ld-elfcomm/common-2f.d: Likewise. * testsuite/ld-elfcomm/common-3a.rd: Likewise. * testsuite/ld-elfcomm/common-3b.rd: Likewise. * testsuite/ld-i386/pr19645.d: Likewise. * testsuite/ld-i386/pr19645.s: Likewise. * testsuite/ld-x86-64/largecomm-1.s: Likewise. * testsuite/ld-x86-64/largecomm-1a.d: Likewise. * testsuite/ld-x86-64/largecomm-1b.d: Likewise. * testsuite/ld-x86-64/largecomm-1c.d: Likewise. * testsuite/ld-x86-64/largecomm-1d.d: Likewise. * testsuite/ld-x86-64/largecomm-1e.d: Likewise. * testsuite/ld-x86-64/largecomm-1f.d: Likewise. * testsuite/ld-x86-64/pr19645.d: Likewise. * testsuite/ld-x86-64/pr19645.s: Likewise. * testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes with assembler. (assembler_generates_commons): Removed. Run -z common/-z nocommon tests. Run *.d tests. * testsuite/ld-i386/i386.exp: Run pr19645. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with assembler. Test STT_COMMON with readelf.
generated by cgit v1.1 at 2024-08-01 15:30:31 +0000