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2024-01-01cpu: or1k: drop unused l.swa flagMike Frysinger3-3/+1
The "flag" argument isn't set/used in this insn, so drop it. This fixes an unused variable warning in the generated sim.
2024-01-01sim: fix pervasive typoTom Tromey9-42/+42
I noticed a typo in a sim constant. This patch fixes it. permenant -> permanent
2024-01-01Automatic date update in version.inGDB Administrator1-1/+1
2023-12-31Run 'black' on tui-window.pyTom Tromey1-2/+4
Mark pointed out that a recent patch of mine caused the buildbot to complain about the formatting of some Python test code. This patch re-runs 'black' to fix the problem.
2023-12-31[gdb/testsuite] Fix typo in gdb.base/catch-syscall.expTom de Vries1-1/+1
On aarch64-linux with a gdb build without libexpat, I run into: ... (gdb) PASS: gdb.base/catch-syscall.exp: determine pipe syscall: \ catch syscall 59 continue Continuing. Catchpoint 5 (call to syscall 59), 0x0000fffff7e04578 in pipe () from \ /lib64/libc.so.6 (gdb) FAIL: gdb.base/catch-syscall.exp: determine pipe syscall: continue ... In the test-case, this pattern handles either the syscall name or number for the pipe syscall: ... -re -wrap "Catchpoint $decimal \\(call to syscall (pipe|$SYS_pipe)\\).*" { ... but the pattern for the pipe2 syscall mistakenly uses SYS_pipe instead of SYS_pipe2: ... -re -wrap "Catchpoint $decimal \\(call to syscall (pipe2|$SYS_pipe)\\).*" { ... and consequently doesn't handle the pipe2 syscall number. Fix the typo by using SYS_pipe2 instead. Tested on aarch64-linux.
2023-12-31Automatic date update in version.inGDB Administrator1-1/+1
2023-12-30Add keywords to TuiWindow.writeTom Tromey2-4/+8
The gdb docs promise that methods with more than two or more arguments will accept keywords. However, I found that TuiWindow.write didn't allow them. This patch adds the missing support.
2023-12-30[gdb/testsuite] Fix gdb.base/gdb-index-err.exp for root userTom de Vries1-1/+7
When running test-case gdb.base/gdb-index-err.exp in a container as root user, I run into: ... FAIL: gdb.base/gdb-index-err.exp: flag=: \ try to write index to a non-writable directory FAIL: gdb.base/gdb-index-err.exp: flag=-dwarf-5: \ try to write index to a non-writable directory ... The test-case creates a directory without write permissions: ... $ ls -ald private dr-xr-xr-x 2 root root 4096 Dec 29 06:26 private/ ... but apparently the root user is still able to write in it. Fix this by making the test unsupported for the root user. Tested on x86_64-linux. Reviewed-By: Lancelot SIX <lancelot.six@amd.com> PR testsuite/31197 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31197
2023-12-30LoongArch: Commas inside double quotesAlan Modra1-1/+5
This adds an extra feature: Commas inside double quotes are not an arg delimiter, and thus can be part of the arg. * loongarch-coder.c (loongarch_split_args_by_comma): Commas inside quotes are not arg delimiters.
2023-12-30Regen bfd-in2.hAlan Modra1-1/+0
Please DON'T edit this file. READ THE COMMENT!
2023-12-30MAINTAINERS: Update my email addressJoseph Myers2-2/+2
There will be another update in January.
2023-12-30Automatic date update in version.inGDB Administrator1-1/+1
2023-12-29x86: Append "#pass" to APX testsH.J. Lu5-0/+5
Append "#pass" to APX tests for targets which pad text sections with NOPs. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Append "#pass". * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Likewise.
2023-12-29x86: Don't use .insn with '/'H.J. Lu1-3/+3
'/' starts a comment for some targets. Use .byte instead of .insn with '/'. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Use .byte instead of .insn with '/'.
2023-12-29Fix x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu1-0/+1
commit 3d5a60de52556f6a53d71d7e607c6696450ae3e4 Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Jun 8 10:01:03 2023 -0700 x86-64: Add R_X86_64_CODE_4_GOTPCRELX added a new field, fx_tcbit3, to fix. But it didn't initialize it. Fix it by clearing it in fix_new_internal. * wrtite.c (fix_new_internal): Clear fx_tcbit3.
2023-12-29dwarf, fortran: add support for DW_TAG_entry_pointNils-Christian Kempke8-5/+479
Fortran provides additional entry points for subroutines and functions. These entry points may use only a subset (or a different set) of the parameters of the original subroutine. The entry points may be described via the DWARF tag DW_TAG_entry_point. This commit adds support for parsing the DW_TAG_entry_point DWARF tag. Currently, between ifx/ifort/gfortran, only ifort is actually emitting this tag. Both, ifx and gfortran use the DW_TAG_subprogram tag as workaround/alternative. Thus, this patch really only adds more ifort support. Even so, some of the attached tests still fail for ifort, due to some wrong line info generated for the entry points in ifort. After this patch it is possible to set a breakpoint in gdb with the ifort compiled example at the entry points 'foo' and 'foobar', which was not possible before. As gcc and ifx do not emit the tag I also added a test to gdb.dwarf2 which uses some underlying c compiled code and adds some Fortran style DWARF to it emitting the DW_TAG_entry_point. Before this patch it was not possible to actually define breakpoint at the entry point tags. For gfortran there actually exists a bug on bugzilla, asking for the use of DW_TAG_entry_point over DW_TAG_subprogram: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=37134 This patch was originally posted here https://sourceware.org/legacy-ml/gdb-patches/2017-07/msg00317.html but its review/pinging got lost after a while. I reworked it to fit the current GDB. Co-authored-by: Bernhard Heckel <bernhard.heckel@intel.com> Co-authored-by: Tim Wiederhake <tim.wiederhake@intel.com> Approved-by: Tom Tromey <tom@tromey.com>
2023-12-29gdb, dwarf: add assert to dwarf2_get_pc_boundsNils-Christian Kempke1-0/+1
In dwarf2_get_pc_bounds we were writing unchecked to *lowpc. This commit adds a gdb_assert to first check that lowpc != nullptr. Approved-by: Tom Tromey <tom@tromey.com>
2023-12-29gdb, dwarf: move part of dwarf2_get_pc_bounds into separate functionNils-Christian Kempke1-21/+50
This commit is in preparation of the next commit. There, we will add a second variation to retrieve the pc bounds for DIEs tagged with DW_TAG_entry_point. Instead of dwarf_get_pc_bounds_ranges_or_highlow_pc we will call a separate method for entry points. As the validity checks at the endo f dwarf2_get_pc_bounds are the same for both variants, we introduced the new dwarf_get_pc_bounds_ranges_or_highlow_pc method, outsourcing part of dwarf2_get_pc_bounds. This commit should have no functional impact on GDB. Approved-by: Tom Tromey <tom@tromey.com>
2023-12-29LoongArch: ld: Add support for tls le relax.changjiachen6-1/+320
Add tls le relax related testsuites in ld. The new test cases are mainly tested in three aspects: 1. tls le relax function correctness test. 2. tls le relax boundary check test. 3. tls le relax function compatibility test. ld/testsuite/ChangeLog: * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. * ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test. * ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise. * ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise.
2023-12-29LoongArch: gas: Add support for tls le relax.changjiachen5-0/+85
Add tls le relax related relocs support and testsuites in gas. The main test is three new relocation items, R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R, R_LARCH_TLS_LE_LO12_R can be generated properly and tls le insn format check. gas/ChangeLog: * config/tc-loongarch.c: (loongarch_args_parser_can_match_arg_helper): Add support for relax. * gas/testsuite/gas/loongarch/reloc.d: Likewise. * gas/testsuite/gas/loongarch/reloc.s: Likewise. * gas/testsuite/gas/loongarch/loongarch.exp: Likewise. * gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test.
2023-12-29LoongArch: opcodes: Add support for tls le relax.changjiachen1-0/+1
Add new opcode for tls le relax. opcode/ChangeLog: * loongarch-opc.c: Add new loongarch opcode.
2023-12-29LoongArch: include: Add support for tls le relax.changjiachen1-0/+12
Add new relocs number for tls le relax. include/ChangeLog: * elf/loongarch.h: (RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number. (RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise. (RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise.
2023-12-29LoongArch: bfd: Add support for tls le relax.changjiachen6-5/+169
Add tls le relax support and related relocs in bfd. New relocation related explanation can refer to the following url: https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc This support does two main things: 1. Implement support for three new relocation items in bfd. The three new relocation items are shown below: R_LARCH_TLS_LE_ADD_R R_LARCH_TLS_LE_HI20_R R_LARCH_TLS_LE_LO12_R 2. ADD a new macro RELOCATE_TLS_TP32_HI20 Handle problems caused by symbol extensions in TLS LE, The processing is similar to the macro RELOCATE_CALC_PC32_HI20 method. 3. Implement the tls le relax function. bfd/ChangeLog: * bfd-in2.h: Add relocs related to tls le relax. * elfnn-loongarch.c: (loongarch_relax_tls_le): New function. (RELOCATE_TLS_TP32_HI20): New macro. (loongarch_elf_check_relocs): Add new reloc support. (perform_relocation): Likewise. (loongarch_elf_relocate_section): Handle new relocs related to relax. (loongarch_elf_relax_section): Likewise. * elfxx-loongarch.c: (LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise. (LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise. * libbfd.h: Add relocs related to tls le relax. * reloc.c: Likewise.
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma3-0/+29
In order to make it easier to complete the compiler's support for the XTheadVector extension and to be as compatible as possible with the programming model of the 'V' extension ([1]), we consider adding a few pseudo instructions ([2]). th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0 th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs Ref: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html [2] https://github.com/T-head-Semi/thead-extension-spec/pull/40 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for new pseudoinstructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Add new pseudoinstructions.
2023-12-29Automatic date update in version.inGDB Administrator1-1/+1
2023-12-28ld: Mention support for Intel APX relocations in NEWSH.J. Lu1-0/+2
2023-12-28Gold: Handle R_X86_64_CODE_4_GOTPC32_TLSDESC/R_X86_64_CODE_4_GOTTPOFFH.J. Lu8-37/+203
Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. Convert add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg to add $name@tpoff, %reg mov $name@tpoff, %reg and lea name@tlsdesc(%rip), %reg to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. elfcpp/ * x86_64.h (R_X86_64_CODE_4_GOTTPOFF): New. (R_X86_64_CODE_4_GOTPC32_TLSDESC): Likewise. gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_4_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_desc_gd_to_ie): Handle R_X86_64_CODE_4_GOTPC32_TLSDESC. (Target_x86_64::Relocate::tls_desc_gd_to_le): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_4_GOTTPOFF. * testsuite/Makefile.am: Add x86_64_ie_to_le test. * testsuite/Makefile.in: Regenerated. * testsuite/x86_64_gd_to_le.s: Add R_X86_64_CODE_4_GOTPC32_TLSDESC test. * testsuite/x86_64_gd_to_le.sh: Check GDesc to LE conversion. * testsuite/x86_64_ie_to_le.s: New file. * testsuite/x86_64_ie_to_le.sh: Likewise.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu14-21/+329
For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
2023-12-28gold: Handle R_X86_64_CODE_4_GOTPCRELXH.J. Lu8-10/+54
Handle R_X86_64_CODE_4_GOTPCRELX and convert mov name@GOTPCREL(%rip), %r31 to lea name@GOTPCREL(%rip), %r31 if the instruction is encoded with the REX2 prefix when possible. elfcpp/ * x86_64.h (R_X86_64_CODE_4_GOTPCRELX): New. gold/ * x86_64.cc (Target_x86_64::can_convert_mov_to_lea): Handle R_X86_64_CODE_4_GOTPCRELX. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::possible_function_pointer_reloc): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. * testsuite/x86_64_mov_to_lea1.s: Add a test for R_X86_64_CODE_4_GOTPCRELX. * testsuite/x86_64_mov_to_lea2.s: Likewise. * testsuite/x86_64_mov_to_lea3.s: Likewise. * testsuite/x86_64_mov_to_lea4.s: Likewise. * testsuite/x86_64_mov_to_lea5.s: Likewise. * testsuite/x86_64_mov_to_lea.sh: Updated.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu19-27/+382
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28gas: Mention initial support for Intel APX in NEWSH.J. Lu1-0/+2
2023-12-28x86: Add NT_X86_SHSTK noteSchimpe, Christina2-0/+5
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to support Intel SHSTK in Linux kernel. For now only userspace shadow stack and kernel IBT are supported by the linux kernel. This note should be used instead of NT_X86_CET introduced in the commit "x86: Add NT_X86_CET note", as it is outdated and only used by old binutils versions.
2023-12-28Support APX JMPABS for disassemblerHu, Lin17-2/+122
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto. opcodes/ChangeLog: * i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs. (print_insn): Add #UD exception for jmpabs. (dis386): Modify a1 unit for support jmpabs. * i386-mnem.h: Regenerated. * i386-opc.tbl: New insns. * i386-tbl.h: Regenerated.
2023-12-28Support APX NDD optimized encoding.Hu, Lin14-0/+362
This patch aims to optimize: add %r16, %r15, %r15 -> add %r16, %r15 gas/ChangeLog: * config/tc-i386.c (check_Rex_required): New function. (can_convert_NDD_to_legacy): Ditto. (match_template): If we can optimzie APX NDD insns, so rematch template. * testsuite/gas/i386/x86-64.exp: Add test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
2023-12-28Support APX pushp/poppCui, Lili12-1062/+1154
gas/ChangeLog: * config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires rex2.w == 1." * testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated.
2023-12-28Support APX Push2/Pop2Mo, Zewei19-1960/+2291
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin114-430/+2102
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Add tests for APX GPR32 with extend evex prefixCui, Lili12-0/+1498
gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't support gpr32. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add new test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili11-4196/+4847
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili2-0/+292
opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili26-11903/+12808
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-28sim: pru: Fix emulation of carry bitDimitar Dimitrov2-4/+424
The PRU architecture documentation [1] was used for the initial GNU simulator implementation. But recently [2] TI confirmed the carry behaviour was wrongly documented. In reality, the PRU carry behaves like the carry in ARM processors. This patch fixes simulator to align with latest recommendations from TI. The new carry.s test was also validated to pass on real hardware - a BeaglePlay board [3]. That test is a bit long because TI still has not released official updates for the PRU documents. And I wanted to ensure simulator handles all edge cases exactly as the real hardware does. [1] https://www.ti.com/lit/pdf/spruij2 [2] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244359/sk-am64b-am64x-pru-assembler-how-works-this-bloody-carry [3] https://www.beagleboard.org/boards/beagleplay Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2023-12-28RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objectsNelson Chu8-15/+89
* Problematic fix commit, 2029e13917d53d2289d3ebb390c4f40bd2112d21 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc *SUB* relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. ld/ * NEWS: Updated. * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with binutils 2.42 and up, to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
2023-12-28Automatic date update in version.inGDB Administrator1-1/+1
2023-12-27asan: buffer overflow in loongarch_elf_rtype_to_howtoAlan Modra1-21/+11
Seen when running ld-loongarch-elf/tlsdesc-dso test. elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for type 'loongarch_reloc_howto_type [124]' So either the loongarch_howto_table needs three more LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure it's worth wasting a little more space to get faster lookup. * elfxx-loongarch.c (loongarch_howto_table): Add LOONGARCH_EMPTY_HOWTO entries for 121..123. (loongarch_elf_rtype_to_howto): Don't support slow lookup. Assert exact table size and r_type indexing. Omit return cast. (loongarch_reloc_name_lookup): Omit assertion and return cast. (loongarch_reloc_type_lookup): Likewise.
2023-12-27PR31191, objcopy leaves temporary filesAlan Modra1-23/+24
Fix the ENOTDIR rmdir too. PR 31191 * objcopy.c (copy_archive): Localise uses of "l". Remove const from name_list.name. Unlink output element on bfd_close error, and NULL list->name to indicate file is removed. Adjust cleanup to prevent rmdir on non-existent file.
2023-12-26sim: common: pull in newlib extensions for Linux compatibilityMike Frysinger2-1/+122
Since newlib allows people to opt-in to extra errno names, pull them into our table too. The values don't conflict with each other -- the newlib names & values are distinct from newlib's Linux compatibility.
2023-12-27Automatic date update in version.inGDB Administrator1-1/+1
2023-12-26Automatic date update in version.inGDB Administrator1-1/+1
2023-12-25binutils: SECURITY: use https URIMike Frysinger1-2/+2
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