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-rw-r--r--opcodes/ChangeLog18
-rw-r--r--opcodes/aarch64-dis.c10
-rw-r--r--opcodes/arc-dis.c2
-rw-r--r--opcodes/arm-dis.c14
-rw-r--r--opcodes/cris-dis.c8
-rw-r--r--opcodes/h8300-dis.c2
-rw-r--r--opcodes/i386-dis.c24
-rw-r--r--opcodes/ia64-gen.c48
-rw-r--r--opcodes/mips-dis.c18
-rw-r--r--opcodes/s390-dis.c6
-rw-r--r--opcodes/wasm32-dis.c4
11 files changed, 86 insertions, 68 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ee67cb5..bd8cfef 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,21 @@
+2021-03-22 Martin Liska <mliska@suse.cz>
+
+ * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
+ * arc-dis.c (parse_option): Likewise.
+ * arm-dis.c (parse_arm_disassembler_options): Likewise.
+ * cris-dis.c (print_with_operands): Likewise.
+ * h8300-dis.c (bfd_h8_disassemble): Likewise.
+ * i386-dis.c (print_insn): Likewise.
+ * ia64-gen.c (fetch_insn_class): Likewise.
+ (parse_resource_users): Likewise.
+ (in_iclass): Likewise.
+ (lookup_specifier): Likewise.
+ (insert_opcode_dependencies): Likewise.
+ * mips-dis.c (parse_mips_ase_option): Likewise.
+ (parse_mips_dis_option): Likewise.
+ * s390-dis.c (disassemble_init_s390): Likewise.
+ * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
+
2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 19482f7..349d7ea 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -58,32 +58,32 @@ static void
parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
{
/* Try to match options that are simple flags */
- if (CONST_STRNEQ (option, "no-aliases"))
+ if (startswith (option, "no-aliases"))
{
no_aliases = 1;
return;
}
- if (CONST_STRNEQ (option, "aliases"))
+ if (startswith (option, "aliases"))
{
no_aliases = 0;
return;
}
- if (CONST_STRNEQ (option, "no-notes"))
+ if (startswith (option, "no-notes"))
{
no_notes = 1;
return;
}
- if (CONST_STRNEQ (option, "notes"))
+ if (startswith (option, "notes"))
{
no_notes = 0;
return;
}
#ifdef DEBUG_AARCH64
- if (CONST_STRNEQ (option, "debug_dump"))
+ if (startswith (option, "debug_dump"))
{
debug_dump = 1;
return;
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 6a6404a..0c9b379 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -795,7 +795,7 @@ parse_option (const char *option)
add_to_decodelist (FLOAT, DP);
add_to_decodelist (FLOAT, CVT);
}
- else if (CONST_STRNEQ (option, "hex"))
+ else if (startswith (option, "hex"))
print_hex = TRUE;
else
/* xgettext:c-format */
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f16a590..9647d00 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -11600,7 +11600,7 @@ parse_arm_disassembler_options (const char *options)
FOR_EACH_DISASSEMBLER_OPTION (opt, options)
{
- if (CONST_STRNEQ (opt, "reg-names-"))
+ if (startswith (opt, "reg-names-"))
{
unsigned int i;
for (i = 0; i < NUM_ARM_OPTIONS; i++)
@@ -11615,11 +11615,11 @@ parse_arm_disassembler_options (const char *options)
opcodes_error_handler (_("unrecognised register name set: %s"),
opt);
}
- else if (CONST_STRNEQ (opt, "force-thumb"))
+ else if (startswith (opt, "force-thumb"))
force_thumb = 1;
- else if (CONST_STRNEQ (opt, "no-force-thumb"))
+ else if (startswith (opt, "no-force-thumb"))
force_thumb = 0;
- else if (CONST_STRNEQ (opt, "coproc"))
+ else if (startswith (opt, "coproc"))
{
const char *procptr = opt + sizeof ("coproc") - 1;
char *endptr;
@@ -11637,10 +11637,10 @@ parse_arm_disassembler_options (const char *options)
continue;
}
endptr += 1;
- if (CONST_STRNEQ (endptr, "generic"))
+ if (startswith (endptr, "generic"))
cde_coprocs &= ~(1 << coproc_number);
- else if (CONST_STRNEQ (endptr, "cde")
- || CONST_STRNEQ (endptr, "CDE"))
+ else if (startswith (endptr, "cde")
+ || startswith (endptr, "CDE"))
cde_coprocs |= (1 << coproc_number);
else
{
diff --git a/opcodes/cris-dis.c b/opcodes/cris-dis.c
index f434249..3f98cb0 100644
--- a/opcodes/cris-dis.c
+++ b/opcodes/cris-dis.c
@@ -786,7 +786,7 @@ print_with_operands (const struct cris_opcode *opcodep,
better way). */
if (opcodep->name[0] == 'j')
{
- if (CONST_STRNEQ (opcodep->name, "jsr"))
+ if (startswith (opcodep->name, "jsr"))
/* It's "jsr" or "jsrc". */
info->insn_type = dis_jsr;
else
@@ -1360,16 +1360,16 @@ print_with_operands (const struct cris_opcode *opcodep,
itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
if (TRACE_CASE && case_offset_counter == 0)
{
- if (CONST_STRNEQ (opcodep->name, "sub"))
+ if (startswith (opcodep->name, "sub"))
case_offset = last_immediate;
/* It could also be an "add", if there are negative case-values. */
- else if (CONST_STRNEQ (opcodep->name, "add"))
+ else if (startswith (opcodep->name, "add"))
/* The first case is the negated operand to the add. */
case_offset = -last_immediate;
/* A bound insn will tell us the number of cases. */
- else if (CONST_STRNEQ (opcodep->name, "bound"))
+ else if (startswith (opcodep->name, "bound"))
no_of_case_offsets = last_immediate + 1;
/* A jump or jsr or branch breaks the chain of insns for a
diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c
index 4cd8e3c..4696235 100644
--- a/opcodes/h8300-dis.c
+++ b/opcodes/h8300-dis.c
@@ -655,7 +655,7 @@ bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
regno[1]);
return qi->length;
}
- if (CONST_STRNEQ (q->name, "mova"))
+ if (startswith (q->name, "mova"))
{
const op_type *args = q->args.nib;
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 4e3304d..9e5c412 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9413,38 +9413,38 @@ print_insn (bfd_vma pc, disassemble_info *info)
for (p = info->disassembler_options; p != NULL; )
{
- if (CONST_STRNEQ (p, "amd64"))
+ if (startswith (p, "amd64"))
isa64 = amd64;
- else if (CONST_STRNEQ (p, "intel64"))
+ else if (startswith (p, "intel64"))
isa64 = intel64;
- else if (CONST_STRNEQ (p, "x86-64"))
+ else if (startswith (p, "x86-64"))
{
address_mode = mode_64bit;
priv.orig_sizeflag |= AFLAG | DFLAG;
}
- else if (CONST_STRNEQ (p, "i386"))
+ else if (startswith (p, "i386"))
{
address_mode = mode_32bit;
priv.orig_sizeflag |= AFLAG | DFLAG;
}
- else if (CONST_STRNEQ (p, "i8086"))
+ else if (startswith (p, "i8086"))
{
address_mode = mode_16bit;
priv.orig_sizeflag &= ~(AFLAG | DFLAG);
}
- else if (CONST_STRNEQ (p, "intel"))
+ else if (startswith (p, "intel"))
{
intel_syntax = 1;
- if (CONST_STRNEQ (p + 5, "-mnemonic"))
+ if (startswith (p + 5, "-mnemonic"))
intel_mnemonic = 1;
}
- else if (CONST_STRNEQ (p, "att"))
+ else if (startswith (p, "att"))
{
intel_syntax = 0;
- if (CONST_STRNEQ (p + 3, "-mnemonic"))
+ if (startswith (p + 3, "-mnemonic"))
intel_mnemonic = 0;
}
- else if (CONST_STRNEQ (p, "addr"))
+ else if (startswith (p, "addr"))
{
if (address_mode == mode_64bit)
{
@@ -9461,14 +9461,14 @@ print_insn (bfd_vma pc, disassemble_info *info)
priv.orig_sizeflag |= AFLAG;
}
}
- else if (CONST_STRNEQ (p, "data"))
+ else if (startswith (p, "data"))
{
if (p[4] == '1' && p[5] == '6')
priv.orig_sizeflag &= ~DFLAG;
else if (p[4] == '3' && p[5] == '2')
priv.orig_sizeflag |= DFLAG;
}
- else if (CONST_STRNEQ (p, "suffix"))
+ else if (startswith (p, "suffix"))
priv.orig_sizeflag |= SUFFIX_ALWAYS;
p = strchr (p, ',');
diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c
index 7f3f0ed..de409bb 100644
--- a/opcodes/ia64-gen.c
+++ b/opcodes/ia64-gen.c
@@ -467,7 +467,7 @@ fetch_insn_class (const char *full_name, int create)
int ind;
int is_class = 0;
- if (CONST_STRNEQ (full_name, "IC:"))
+ if (startswith (full_name, "IC:"))
{
name = xstrdup (full_name + 3);
is_class = 1;
@@ -746,7 +746,7 @@ parse_resource_users (const char *ref, int **usersp, int *nusersp,
are read. Only create new classes if it's *not* an insn class,
or if it's a composite class (which wouldn't necessarily be in the IC
table). */
- if (! CONST_STRNEQ (name, "IC:") || xsect != NULL)
+ if (! startswith (name, "IC:") || xsect != NULL)
create = 1;
iclass = fetch_insn_class (name, create);
@@ -1039,7 +1039,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
if (ic->comment)
{
- if (CONST_STRNEQ (ic->comment, "Format"))
+ if (startswith (ic->comment, "Format"))
{
/* Assume that the first format seen is the most restrictive, and
only keep a later one if it looks like it's more restrictive. */
@@ -1055,7 +1055,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
else
format = ic->comment;
}
- else if (CONST_STRNEQ (ic->comment, "Field"))
+ else if (startswith (ic->comment, "Field"))
{
if (field)
warn (_("overlapping field %s->%s\n"),
@@ -1069,7 +1069,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
instructions. */
if (ic->nsubs == 0 && ic->nxsubs == 0)
{
- int is_mov = CONST_STRNEQ (idesc->name, "mov");
+ int is_mov = startswith (idesc->name, "mov");
int plain_mov = strcmp (idesc->name, "mov") == 0;
int len = strlen(ic->name);
@@ -1128,32 +1128,32 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
if (resolved && format)
{
- if (CONST_STRNEQ (idesc->name, "dep")
+ if (startswith (idesc->name, "dep")
&& strstr (format, "I13") != NULL)
resolved = idesc->operands[1] == IA64_OPND_IMM8;
- else if (CONST_STRNEQ (idesc->name, "chk")
+ else if (startswith (idesc->name, "chk")
&& strstr (format, "M21") != NULL)
resolved = idesc->operands[0] == IA64_OPND_F2;
- else if (CONST_STRNEQ (idesc->name, "lfetch"))
+ else if (startswith (idesc->name, "lfetch"))
resolved = (strstr (format, "M14 M15") != NULL
&& (idesc->operands[1] == IA64_OPND_R2
|| idesc->operands[1] == IA64_OPND_IMM9b));
- else if (CONST_STRNEQ (idesc->name, "br.call")
+ else if (startswith (idesc->name, "br.call")
&& strstr (format, "B5") != NULL)
resolved = idesc->operands[1] == IA64_OPND_B2;
- else if (CONST_STRNEQ (idesc->name, "br.call")
+ else if (startswith (idesc->name, "br.call")
&& strstr (format, "B3") != NULL)
resolved = idesc->operands[1] == IA64_OPND_TGT25c;
- else if (CONST_STRNEQ (idesc->name, "brp")
+ else if (startswith (idesc->name, "brp")
&& strstr (format, "B7") != NULL)
resolved = idesc->operands[0] == IA64_OPND_B2;
else if (strcmp (ic->name, "invala") == 0)
resolved = strcmp (idesc->name, ic->name) == 0;
- else if (CONST_STRNEQ (idesc->name, "st")
+ else if (startswith (idesc->name, "st")
&& (strstr (format, "M5") != NULL
|| strstr (format, "M10") != NULL))
resolved = idesc->flags & IA64_OPCODE_POSTINC;
- else if (CONST_STRNEQ (idesc->name, "ld")
+ else if (startswith (idesc->name, "ld")
&& (strstr (format, "M2 M3") != NULL
|| strstr (format, "M12") != NULL
|| strstr (format, "M7 M8") != NULL))
@@ -1166,7 +1166,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
plain brl matches brl.cond. */
if (!resolved
&& (strcmp (idesc->name, "brl") == 0
- || CONST_STRNEQ (idesc->name, "brl."))
+ || startswith (idesc->name, "brl."))
&& strcmp (ic->name, "brl.cond") == 0)
{
resolved = 1;
@@ -1175,7 +1175,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
/* Misc br variations ('.cond' is optional). */
if (!resolved
&& (strcmp (idesc->name, "br") == 0
- || CONST_STRNEQ (idesc->name, "br."))
+ || startswith (idesc->name, "br."))
&& strcmp (ic->name, "br.cond") == 0)
{
if (format)
@@ -1188,7 +1188,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
}
/* probe variations. */
- if (!resolved && CONST_STRNEQ (idesc->name, "probe"))
+ if (!resolved && startswith (idesc->name, "probe"))
{
resolved = strcmp (ic->name, "probe") == 0
&& !((strstr (idesc->name, "fault") != NULL)
@@ -1222,7 +1222,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
}
/* Some variants of mov and mov.[im]. */
- if (!resolved && CONST_STRNEQ (ic->name, "mov_"))
+ if (!resolved && startswith (ic->name, "mov_"))
resolved = in_iclass_mov_x (idesc, ic, format, field);
}
@@ -1487,13 +1487,13 @@ lookup_specifier (const char *name)
warn (_("Don't know how to specify # dependency %s\n"),
name);
}
- else if (CONST_STRNEQ (name, "AR[FPSR]"))
+ else if (startswith (name, "AR[FPSR]"))
return IA64_RS_AR_FPSR;
- else if (CONST_STRNEQ (name, "AR["))
+ else if (startswith (name, "AR["))
return IA64_RS_ARX;
- else if (CONST_STRNEQ (name, "CR["))
+ else if (startswith (name, "CR["))
return IA64_RS_CRX;
- else if (CONST_STRNEQ (name, "PSR."))
+ else if (startswith (name, "PSR."))
return IA64_RS_PSR;
else if (strcmp (name, "InService*") == 0)
return IA64_RS_INSERVICE;
@@ -2444,7 +2444,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
int j;
if (strcmp (opc->name, "cmp.eq.and") == 0
- && CONST_STRNEQ (rs->name, "PR%")
+ && startswith (rs->name, "PR%")
&& rs->mode == 1)
no_class_found = 99;
@@ -2455,7 +2455,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note))
{
/* We can ignore ic_note 11 for non PR resources. */
- if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR"))
+ if (ic_note == 11 && ! startswith (rs->name, "PR"))
ic_note = 0;
if (ic_note != 0 && rs->regnotes[j] != 0
@@ -2483,7 +2483,7 @@ insert_opcode_dependencies (struct ia64_opcode *opc,
if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note))
{
/* We can ignore ic_note 11 for non PR resources. */
- if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR"))
+ if (ic_note == 11 && ! startswith (rs->name, "PR"))
ic_note = 0;
if (ic_note != 0 && rs->chknotes[j] != 0
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 317ced5..d1f73b4 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -923,7 +923,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
static bfd_boolean
parse_mips_ase_option (const char *option)
{
- if (CONST_STRNEQ (option, "msa"))
+ if (startswith (option, "msa"))
{
mips_ase |= ASE_MSA;
if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
@@ -934,7 +934,7 @@ parse_mips_ase_option (const char *option)
return TRUE;
}
- if (CONST_STRNEQ (option, "virt"))
+ if (startswith (option, "virt"))
{
mips_ase |= ASE_VIRT;
if (mips_isa & ISA_MIPS64R2
@@ -945,38 +945,38 @@ parse_mips_ase_option (const char *option)
return TRUE;
}
- if (CONST_STRNEQ (option, "xpa"))
+ if (startswith (option, "xpa"))
{
mips_ase |= ASE_XPA;
return TRUE;
}
- if (CONST_STRNEQ (option, "ginv"))
+ if (startswith (option, "ginv"))
{
mips_ase |= ASE_GINV;
return TRUE;
}
- if (CONST_STRNEQ (option, "loongson-mmi"))
+ if (startswith (option, "loongson-mmi"))
{
mips_ase |= ASE_LOONGSON_MMI;
return TRUE;
}
- if (CONST_STRNEQ (option, "loongson-cam"))
+ if (startswith (option, "loongson-cam"))
{
mips_ase |= ASE_LOONGSON_CAM;
return TRUE;
}
/* Put here for match ext2 frist */
- if (CONST_STRNEQ (option, "loongson-ext2"))
+ if (startswith (option, "loongson-ext2"))
{
mips_ase |= ASE_LOONGSON_EXT2;
return TRUE;
}
- if (CONST_STRNEQ (option, "loongson-ext"))
+ if (startswith (option, "loongson-ext"))
{
mips_ase |= ASE_LOONGSON_EXT;
return TRUE;
@@ -994,7 +994,7 @@ parse_mips_dis_option (const char *option, unsigned int len)
const struct mips_arch_choice *chosen_arch;
/* Try to match options that are simple flags */
- if (CONST_STRNEQ (option, "no-aliases"))
+ if (startswith (option, "no-aliases"))
{
no_aliases = 1;
return;
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 1eb3725..4708b09 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -65,11 +65,11 @@ disassemble_init_s390 (struct disassemble_info *info)
for (p = info->disassembler_options; p != NULL; )
{
- if (CONST_STRNEQ (p, "esa"))
+ if (startswith (p, "esa"))
current_arch_mask = 1 << S390_OPCODE_ESA;
- else if (CONST_STRNEQ (p, "zarch"))
+ else if (startswith (p, "zarch"))
current_arch_mask = 1 << S390_OPCODE_ZARCH;
- else if (CONST_STRNEQ (p, "insnlength"))
+ else if (startswith (p, "insnlength"))
option_use_insn_len_bits_p = 1;
else
/* xgettext:c-format */
diff --git a/opcodes/wasm32-dis.c b/opcodes/wasm32-dis.c
index 2fe5132..6926661 100644
--- a/opcodes/wasm32-dis.c
+++ b/opcodes/wasm32-dis.c
@@ -120,9 +120,9 @@ parse_wasm32_disassembler_options (struct disassemble_info *info,
while (opts != NULL)
{
- if (CONST_STRNEQ (opts, "registers"))
+ if (startswith (opts, "registers"))
private->print_registers = TRUE;
- else if (CONST_STRNEQ (opts, "globals"))
+ else if (startswith (opts, "globals"))
private->print_well_known_globals = TRUE;
opts = strchr (opts, ',');
generated by cgit v1.1 at 2024-07-20 07:54:59 +0000