diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/microblaze-opc.h | 33 | ||||
| -rw-r--r-- | opcodes/microblaze-opcm.h | 4 |
2 files changed, 20 insertions, 17 deletions
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 94048e6..7c70c80 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -74,24 +74,25 @@ #define IMMVAL_MASK_MTS 0x4000 #define IMMVAL_MASK_MFS 0x0000 -#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ -#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ -#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ -#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ -#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */ -#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits +#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ +#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ +#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ +#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */ +#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits and last nibble of last byte for spr. */ -#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last +#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr. */ -#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */ -#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */ -#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ +#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */ +#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */ +#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ -#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ -#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ -#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ -#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ +#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ +#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ +#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ /* New Mask for msrset, msrclr insns. */ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ @@ -101,7 +102,7 @@ #define DELAY_SLOT 1 #define NO_DELAY_SLOT 0 -#define MAX_OPCODES 289 +#define MAX_OPCODES 291 const struct op_code_struct { @@ -174,7 +175,9 @@ const struct op_code_struct {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, + {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, + {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst }, {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 4cf6f07..92c245d 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -33,8 +33,8 @@ enum microblaze_instr /* 'or/and/xor' are C++ keywords. */ microblaze_or, microblaze_and, microblaze_xor, andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, - wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd, - brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, + wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br, + brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, |