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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/mips-opc.c6
2 files changed, 9 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ea0eeef..9a24e89 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
+ macros before their corresponding MIPS III hardware instructions.
+
2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6dc615f..230d0f8 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -743,8 +743,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
-{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
+/* The macro has to be first to handle o32 correctly. */
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
@@ -1173,8 +1174,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
-{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
+/* The macro has to be first to handle o32 correctly. */
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },