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-rw-r--r--opcodes/or1k-desc.c66
1 files changed, 33 insertions, 33 deletions
diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c
index 5bbb513..f442cc2 100644
--- a/opcodes/or1k-desc.c
+++ b/opcodes/or1k-desc.c
@@ -1008,127 +1008,127 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sys-sr: supervision register */
{ "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-esr0: exception supervision register 0 */
{ "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-epcr0: exception PC register 0 */
{ "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-lee: SR little endian enable bit */
{ "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-f: SR flag bit */
{ "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-cy: SR carry bit */
{ "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-ov: SR overflow bit */
{ "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-sr-ove: SR overflow exception enable bit */
{ "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
{ "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-cpucfgr-nd: CPUCFGR no delay bit */
{ "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sys-fpcsr-rm: floating point round mode */
{ "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* mac-machi: MAC HI result register */
{ "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* mac-maclo: MAC LO result register */
{ "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* atomic-reserve: atomic reserve flag */
{ "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* atomic-address: atomic address */
{ "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* uimm6: uimm6 */
{ "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rD: destination register */
{ "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rA: source register A */
{ "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rB: source register B */
{ "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* disp26: pc-rel 26 bit */
{ "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* simm16: 16-bit signed immediate */
{ "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* uimm16: 16-bit unsigned immediate */
{ "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* simm16-split: split 16-bit signed immediate */
{ "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16,
- { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* uimm16-split: split 16-bit unsigned immediate */
{ "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16,
- { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rDSF: destination register (single floating point mode) */
{ "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rASF: source register A (single floating point mode) */
{ "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rBSF: source register B (single floating point mode) */
{ "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rDDF: destination register (double floating point mode) */
{ "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rADF: source register A (double floating point mode) */
{ "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* rBDF: source register B (double floating point mode) */
{ "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@@ -2051,7 +2051,7 @@ or1k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
@@ -2091,7 +2091,7 @@ or1k_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
generated by cgit v1.1 at 2024-08-18 22:39:27 +0000