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-rw-r--r--opcodes/fr30-desc.c102
1 files changed, 51 insertions, 51 deletions
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index b6db90c..0788bc2 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -364,199 +364,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
- { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@@ -1689,7 +1689,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
@@ -1729,7 +1729,7 @@ fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
generated by cgit v1.1 at 2024-07-01 06:16:47 +0000