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-rw-r--r--gas/NEWS3
-rw-r--r--gas/config/tc-riscv.c6
2 files changed, 6 insertions, 3 deletions
diff --git a/gas/NEWS b/gas/NEWS
index 53b8759..643f0e6 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
-*- text -*-
+* On RISC-V macro instructions expanding to AUIPC and a load, store, or branch
+ no longer accept x0 as an intermediate and/or destination register.
+
* Add support for Reliability, Availability and Serviceability extension v2
(RASv2) for AArch64.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index af9a34a..3222bd1 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2531,11 +2531,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
switch (*oparg)
{
case '\0': /* End of args. */
+ if (insn->match_func && !insn->match_func (insn, ip->insn_opcode))
+ break;
+
if (insn->pinfo != INSN_MACRO)
{
- if (!insn->match_func (insn, ip->insn_opcode))
- break;
-
/* For .insn, insn->match and insn->mask are 0. */
if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
? ip->insn_opcode