diff options
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/arm/attr-march-armv8_6-a.d | 17 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-bad.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-bad.l | 112 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-bad.s | 119 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-cmdline-bad-2.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-cmdline-bad-3.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-cmdline-bad.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-neon.s | 53 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-non-neon.s | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-thumb-bad.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-thumb-bad.l | 112 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-thumb.d | 44 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16-vfp.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16.d | 39 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/bfloat16.s | 2 |
15 files changed, 544 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8_6-a.d b/gas/testsuite/gas/arm/attr-march-armv8_6-a.d new file mode 100644 index 0000000..73bcbaf --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8_6-a.d @@ -0,0 +1,17 @@ +# name: attributes for -march=armv8.6-a +# source: blank.s +# as: -march=armv8.6-a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8.6-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_Advanced_SIMD_arch: NEON for ARMv8.1 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/bfloat16-bad.d b/gas/testsuite/gas/arm/bfloat16-bad.d new file mode 100644 index 0000000..95f266d --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-bad.d @@ -0,0 +1,4 @@ +#name: Bfloat 16 failure cases +#source: bfloat16-bad.s +#as: -mno-warn-deprecated -march=armv8.6-a+simd +#error_output: bfloat16-bad.l diff --git a/gas/testsuite/gas/arm/bfloat16-bad.l b/gas/testsuite/gas/arm/bfloat16-bad.l new file mode 100644 index 0000000..242e538 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-bad.l @@ -0,0 +1,112 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vdot.b16 d0,d0,d0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vmmla q0.b16,q0,q0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vdot.bf32 d0,d0,d0\[1\]' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vdot d0.bf32,d0,d0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vdot d0.bf32,d0.bf16,d0.bf16' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne d0,d0,d0' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne d0,d0,d0\[1\]' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vmmlane q0,q0,q0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmatne.bf16 q0,d0,d0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmatne.bf16 q0,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vfmabne.bf16 q0,d0,d0' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vfmabne.bf16 q0,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vcvtne.bf16.f32 d0,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d32,d0,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d32,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d0,d32' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d32,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 16 -- `vdot d0,d0,d16\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vcvtne.bf16.f32 d32,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q16,q0,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q16,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q0,q16' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q16,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q16,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q16,q0,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q16,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q0,q16' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab.bf16 q16,d0,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab.bf16 q16,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab.bf16 q0,q32,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab.bf16 q0,q32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 8 -- `vfmab.bf16 q0,q0,d8\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat.bf16 q16,d0,d0' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat.bf16 q16,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat.bf16 q0,q32,d0' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat.bf16 q0,q32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 8 -- `vfmat.bf16 q0,q0,d8\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vcvt.bf16.f32 d0,q16' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot q0,q0,d5' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot q0,d5,q0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot d5,q0,q0' +[^ :]+:[0-9]+: Error: only D registers may be indexed -- `vdot q0,d5,q0\[0\]' +[^ :]+:[0-9]+: Error: only D registers may be indexed -- `vdot d5,q0,q0\[0\]' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q0,d5' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,d5,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla d5,q0,q0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmab.bf16 d0,q0,d0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmab.bf16 d0,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmat.bf16 d0,q0,d0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmat.bf16 d0,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: operand size must match register width +[^ :]+:[0-9]+: Error: invalid neon suffix for non neon instruction +[^ :]+:[0-9]+: Error: index must be 0 or 1 -- `vdot q0,q0,d0\[2\]' +[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmab.bf16 q0,d0,d0\[4\]' +[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmat.bf16 q0,d0,d0\[4\]' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvtb.b16.f32 s0,s0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvtb.bf32.f32 s0,s0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0.b16,s0.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0.bf32,s0.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb s0.f32,s0.bf16' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvtt.b16.f32 s0,s0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvtt.bf32.f32 s0,s0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0.b16,s0.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0.bf32,s0.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt s0.f32,s0.bf16' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvt.b16.f32 d0,q0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvt.bf32.f32 d0,q0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0.b16,q0.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0.bf32,q0.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvt d0.f32,q0.bf16' +[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtt.bf16.f32 s0,s0,#0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtt.bf16.f32 s0,s0,#1' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt.bf16.f32 d0,s0' +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt.bf16.f32 s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt.bf16.f32 s0,s0,s0,s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt.bf16.f32 s0,s0,s0' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt.bf16.f32 s0,s32' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt.bf16.f32 s32,s32' +[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtb.bf16.f32 s0,s0,#0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtb.bf16.f32 s0,s0,#1' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb.bf16.f32 d0,s0' +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb.bf16.f32 s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb.bf16.f32 s0,s0,s0,s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb.bf16.f32 s0,s0,s0' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb.bf16.f32 s0,s32' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb.bf16.f32 s32,s32' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vcvtne.bf16.f32 d0,q0' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne.bf16 d0,d20,d11' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne.bf16 d0,d20,d11\[1\]' +[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vmmlane.bf16 q0,q0,q0' +[^ :]+:[0-9]+: Error: IT falling in the range of a previous IT block -- `ittt ne' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdot.bf16 d0,d20,d11' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdot.bf16 d0,d20,d11\[1\]' diff --git a/gas/testsuite/gas/arm/bfloat16-bad.s b/gas/testsuite/gas/arm/bfloat16-bad.s new file mode 100644 index 0000000..f6db1ff --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-bad.s @@ -0,0 +1,119 @@ +.syntax unified + +// Test warnings about type specifier being incorrect. +vdot.b16 d0, d0, d0 +vmmla q0.b16, q0, q0 +vdot.bf32 d0, d0, d0[1] +vdot d0.bf32, d0, d0 +vdot d0.bf32, d0.bf16, d0.bf16 + +// Test conditions are not allowed in ARM. +vdotne d0, d0, d0 +vdotne d0, d0, d0[1] +vmmlane q0, q0, q0 +vfmatne.bf16 q0, d0, d0 +vfmatne.bf16 q0, d0, d0[0] +vfmabne.bf16 q0, d0, d0 +vfmabne.bf16 q0, d0, d0[0] +vcvtne.bf16.f32 d0, q0 + +// d register out of range +vdot d32, d0, d0 +vdot d0, d32, d0 +vdot d0, d0, d32 +vdot d32, d0, d0[0] +vdot d0, d32, d0[0] +vdot d0, d0, d16[0] +vcvtne.bf16.f32 d32, q0 + +// q register out of range +vdot q16, q0, q0 +vdot q0, q16, q0 +vdot q0, q0, q16 +vdot q16, q0, d0[0] +vdot q0, q16, d0[0] +vmmla q16, q0, q0 +vmmla q0, q16, q0 +vmmla q0, q0, q16 +vfmab.bf16 q16, d0, d0 +vfmab.bf16 q16, d0, d0[0] +vfmab.bf16 q0, q32, d0 +vfmab.bf16 q0, q32, d0[0] +vfmab.bf16 q0, q0, d8[0] +vfmat.bf16 q16, d0, d0 +vfmat.bf16 q16, d0, d0[0] +vfmat.bf16 q0, q32, d0 +vfmat.bf16 q0, q32, d0[0] +vfmat.bf16 q0, q0, d8[0] +vcvt.bf16.f32 d0, q16 + +// Incorrect set of arguments +vdot q0, q0, d5 +vdot q0, d5, q0 +vdot d5, q0, q0 +vdot q0, d5, q0[0] +vdot d5, q0, q0[0] +vmmla q0, q0, d5 +vmmla q0, d5, q0 +vmmla d5, q0, q0 +vfmab.bf16 d0, q0, d0 +vfmab.bf16 d0, q0, d0[0] +vfmat.bf16 d0, q0, d0 +vfmat.bf16 d0, q0, d0[0] +vcvt.bf16.f32 q0, d0 + +// vdot index out of range +vdot q0, q0, d0[2] + +// vfma<bt> index out of range +vfmab.bf16 q0, d0, d0[4] +vfmat.bf16 q0, d0, d0[4] + +// Non neon encodings (this file gets assembled more than once but with +// different flags, providing different error messages each time). + +// Type specifier warnings +.macro conversion_type_specifier_check insn, dest, source +\insn\().b16.f32 \dest, \source +\insn\().bf32.f32 \dest, \source +\insn \dest\().b16, \source\().f32 +\insn \dest\().bf32, \source\().f32 +\insn \dest\().f32, \source\().bf16 +.endm + +conversion_type_specifier_check vcvtb, s0, s0 +conversion_type_specifier_check vcvtt, s0, s0 +conversion_type_specifier_check vcvt, d0, q0 + +// Conditions allowed (and checked in the "Valid" source file). + +// Incorrect set of operands & registers out of range +.macro bad_args insn +\insn\().bf16.f32 s0, s0, #0 +\insn\().bf16.f32 s0, s0, #1 +\insn\().bf16.f32 d0, s0 +\insn\().bf16.f32 s0 +\insn\().bf16.f32 s0, s0, s0, s0 +\insn\().bf16.f32 s0, s0, s0 +\insn\().bf16.f32 s0, s32 +\insn\().bf16.f32 s32, s32 +.endm +bad_args vcvtt +bad_args vcvtb + +// Allowed in thumb mode but not allowed in arm mode. +it ne +vcvtne.bf16.f32 d0, q0 + +// Ensure these instructions are not allowed to have a conditional suffix. +ittt ne +vdotne.bf16 d0, d20, d11 +vdotne.bf16 d0, d20, d11[1] +vmmlane.bf16 q0, q0, q0 + +// Ensure we are warned these instructions are UNPREDICTABLE in an IT block in +// thumb. +ittt ne +vdot.bf16 d0, d20, d11 +vdot.bf16 d0, d20, d11[1] +vmmla.bf16 q0, q0, q0 diff --git a/gas/testsuite/gas/arm/bfloat16-cmdline-bad-2.d b/gas/testsuite/gas/arm/bfloat16-cmdline-bad-2.d new file mode 100644 index 0000000..d13b864 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-cmdline-bad-2.d @@ -0,0 +1,4 @@ +#name: Bfloat 16 bad processor +#source: bfloat16-non-neon.s +#as: -mno-warn-deprecated -march=armv8.5-a+simd +#error: .*Error: selected processor does not support bf16 instruction.* diff --git a/gas/testsuite/gas/arm/bfloat16-cmdline-bad-3.d b/gas/testsuite/gas/arm/bfloat16-cmdline-bad-3.d new file mode 100644 index 0000000..5dfdeb4 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-cmdline-bad-3.d @@ -0,0 +1,4 @@ +#name: Bfloat 16 bad extension +#source: bfloat16-non-neon.s +#as: -mno-warn-deprecated -march=armv8.1-a+bf16 +#error: .*Error: extension does not apply to the base architecture.* diff --git a/gas/testsuite/gas/arm/bfloat16-cmdline-bad.d b/gas/testsuite/gas/arm/bfloat16-cmdline-bad.d new file mode 100644 index 0000000..34b8a96 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-cmdline-bad.d @@ -0,0 +1,5 @@ +#name: Bfloat 16 bad FPU +#source: bfloat16-neon.s +#as: -mno-warn-deprecated -mfpu=vfpxd -march=armv8.6-a +#error: .*Error: selected FPU does not support instruction.* + diff --git a/gas/testsuite/gas/arm/bfloat16-neon.s b/gas/testsuite/gas/arm/bfloat16-neon.s new file mode 100644 index 0000000..6f42265 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-neon.s @@ -0,0 +1,53 @@ +.syntax unified +// Check argument encoding by having different arguments. +// We use 20 and 11 since their binary encoding is 10100 and 01011 +// respectively which ensures that we distinguish between the D/M/N bit +// encoding the first or last bit of the argument. +// q registers are encoded as double their actual number. +vdot.bf16 d0, d20, d11 +vdot d11.bf16, d0.bf16, d20.bf16 + +.macro conversion_type_specifier_check insn, dest, source +\insn\().bf16.f32 \dest, \source +\insn \dest\().bf16, \source\().f32 +\insn \dest\().bf16, \source\().f32 +.endm +conversion_type_specifier_check vcvtt,s0,s0 +conversion_type_specifier_check vcvtb,s0,s0 +conversion_type_specifier_check vcvt,d0,q0 + + +// Here we follow the same encoding sequence as above. +// Since the 'M' bit encodes the index and the last register is encoded in 4 +// bits that argument has a different number. +vdot.bf16 d11, d0, d4[1] +vdot d0.bf16, d20.bf16, d11.bf16[0] + +// vmmla only works on q registers. +// These registers are encoded as double the number given in the mnemonic. +// Hence we choose different numbers to ensure a similar bit pattern as above. +// 10 & 5 produce the bit patterns 10100 & 01010 +vmmla.bf16 q10, q5, q0 +vmmla q5.bf16, q0.bf16, q10.bf16 + +vfmat.bf16 q10, q11, q0 +vfmat.bf16 q10, q11, d0[3] +vfmat.bf16 q10, q11, d0[0] + +vfmab.bf16 q10, q11, q0 +vfmab.bf16 q10, q11, d0[3] +vfmab.bf16 q10, q11, d0[0] + +// vcvt +// - no condition allowed in arm +// - no condition allowed in thumb outside IT block +// - Condition *allowed* in thumb in IT block +// - different encoding between thumb and arm +vcvt.bf16.f32 d20, q5 +vcvt.bf16.f32 d11, q10 + +// Only works for thumb mode. +.ifdef COMPILING_FOR_THUMB +it ne +vcvtne.bf16.f32 d0, q0 +.endif diff --git a/gas/testsuite/gas/arm/bfloat16-non-neon.s b/gas/testsuite/gas/arm/bfloat16-non-neon.s new file mode 100644 index 0000000..95e3c3b --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-non-neon.s @@ -0,0 +1,9 @@ +.syntax unified +vcvtb.bf16.f32 s20, s11 +it ne +vcvtbne.bf16.f32 s11, s20 +vcvtbal.bf16.f32 s0, s0 +vcvtt.bf16.f32 s20, s11 +it ne +vcvttne.bf16.f32 s11, s20 +vcvttal.bf16.f32 s0, s0 diff --git a/gas/testsuite/gas/arm/bfloat16-thumb-bad.d b/gas/testsuite/gas/arm/bfloat16-thumb-bad.d new file mode 100644 index 0000000..8322cf0 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-thumb-bad.d @@ -0,0 +1,4 @@ +#name: Bfloat 16 Thumb failure cases +#source: bfloat16-bad.s +#as: -mno-warn-deprecated -mthumb -march=armv8.6-a+simd +#error_output: bfloat16-thumb-bad.l diff --git a/gas/testsuite/gas/arm/bfloat16-thumb-bad.l b/gas/testsuite/gas/arm/bfloat16-thumb-bad.l new file mode 100644 index 0000000..adfcf6f --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-thumb-bad.l @@ -0,0 +1,112 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vdot\.b16 d0,d0,d0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vmmla q0\.b16,q0,q0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vdot\.bf32 d0,d0,d0\[1\]' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vdot d0\.bf32,d0,d0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vdot d0\.bf32,d0\.bf16,d0\.bf16' +[^ :]+:[0-9]+: Error: operand types can't be inferred -- `vdotne d0,d0,d0' +[^ :]+:[0-9]+: Error: operand types can't be inferred -- `vdotne d0,d0,d0\[1\]' +[^ :]+:[0-9]+: Error: operand types can't be inferred -- `vmmlane q0,q0,q0' +[^ :]+:[0-9]+: Error: thumb conditional instruction should be in IT block -- `vfmatne\.bf16 q0,d0,d0' +[^ :]+:[0-9]+: Error: thumb conditional instruction should be in IT block -- `vfmatne\.bf16 q0,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: thumb conditional instruction should be in IT block -- `vfmabne\.bf16 q0,d0,d0' +[^ :]+:[0-9]+: Error: thumb conditional instruction should be in IT block -- `vfmabne\.bf16 q0,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: thumb conditional instruction should be in IT block -- `vcvtne\.bf16\.f32 d0,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d32,d0,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d32,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d0,d32' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d32,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot d0,d32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 16 -- `vdot d0,d0,d16\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vcvtne\.bf16\.f32 d32,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q16,q0,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q16,q0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q0,q16' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q16,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vdot q0,q16,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q16,q0,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q16,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q0,q16' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab\.bf16 q16,d0,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab\.bf16 q16,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab\.bf16 q0,q32,d0' +[^ :]+:[0-9]+: Error: Neon double or quad precision register expected -- `vfmab\.bf16 q0,q32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 8 -- `vfmab\.bf16 q0,q0,d8\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat\.bf16 q16,d0,d0' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat\.bf16 q16,d0,d0\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat\.bf16 q0,q32,d0' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vfmat\.bf16 q0,q32,d0\[0\]' +[^ :]+:[0-9]+: Error: indexed register must be less than 8 -- `vfmat\.bf16 q0,q0,d8\[0\]' +[^ :]+:[0-9]+: Error: VFP single, double or Neon quad precision register expected -- `vcvt\.bf16\.f32 d0,q16' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot q0,q0,d5' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot q0,d5,q0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vdot d5,q0,q0' +[^ :]+:[0-9]+: Error: only D registers may be indexed -- `vdot q0,d5,q0\[0\]' +[^ :]+:[0-9]+: Error: only D registers may be indexed -- `vdot d5,q0,q0\[0\]' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,q0,d5' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla q0,d5,q0' +[^ :]+:[0-9]+: Error: Neon quad precision register expected -- `vmmla d5,q0,q0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmab\.bf16 d0,q0,d0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmab\.bf16 d0,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmat\.bf16 d0,q0,d0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vfmat\.bf16 d0,q0,d0\[0\]' +[^ :]+:[0-9]+: Error: operand size must match register width +[^ :]+:[0-9]+: Error: invalid neon suffix for non neon instruction +[^ :]+:[0-9]+: Error: index must be 0 or 1 -- `vdot q0,q0,d0\[2\]' +[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmab\.bf16 q0,d0,d0\[4\]' +[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmat\.bf16 q0,d0,d0\[4\]' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvtb\.b16\.f32 s0,s0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvtb\.bf32\.f32 s0,s0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0\.b16,s0\.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0\.bf32,s0\.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb s0\.f32,s0\.bf16' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvtt\.b16\.f32 s0,s0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvtt\.bf32\.f32 s0,s0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0\.b16,s0\.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0\.bf32,s0\.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt s0\.f32,s0\.bf16' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad instruction `vcvt\.b16\.f32 d0,q0' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad instruction `vcvt\.bf32\.f32 d0,q0' +[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\? +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0\.b16,q0\.f32' +[^ :]+:[0-9]+: Error: bad size 32 in type specifier +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0\.bf32,q0\.f32' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvt d0\.f32,q0\.bf16' +[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtt\.bf16\.f32 s0,s0,#0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtt\.bf16\.f32 s0,s0,#1' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt\.bf16\.f32 d0,s0' +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt\.bf16\.f32 s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt\.bf16\.f32 s0,s0,s0,s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt\.bf16\.f32 s0,s0,s0' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt\.bf16\.f32 s0,s32' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt\.bf16\.f32 s32,s32' +[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtb\.bf16\.f32 s0,s0,#0' +[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtb\.bf16\.f32 s0,s0,#1' +[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb\.bf16\.f32 d0,s0' +[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb\.bf16\.f32 s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb\.bf16\.f32 s0,s0,s0,s0' +[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb\.bf16\.f32 s0,s0,s0' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb\.bf16\.f32 s0,s32' +[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb\.bf16\.f32 s32,s32' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdotne\.bf16 d0,d20,d11' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdotne\.bf16 d0,d20,d11\[1\]' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vmmlane\.bf16 q0,q0,q0' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdot\.bf16 d0,d20,d11' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdot\.bf16 d0,d20,d11\[1\]' +[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vmmla\.bf16 q0,q0,q0' + diff --git a/gas/testsuite/gas/arm/bfloat16-thumb.d b/gas/testsuite/gas/arm/bfloat16-thumb.d new file mode 100644 index 0000000..cf70d16 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-thumb.d @@ -0,0 +1,44 @@ +#name: Bfloat 16 extension Thumb +#source: bfloat16.s +#as: -mno-warn-deprecated --defsym COMPILING_FOR_THUMB=1 -mthumb -march=armv8.6-a+simd -I$srcdir/$subdir +#objdump: -dr --show-raw-insn +#skip: *-*-pe *-*-wince + +.*: +file format .*arm.* + +Disassembly of section .text: + +00000000 <\.text>: + *[0-9a-f]+: fc04 0d8b vdot\.bf16 d0, d20, d11 + *[0-9a-f]+: fc00 bd24 vdot\.bf16 d11, d0, d20 + *[0-9a-f]+: eeb3 09c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 09c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 09c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 0940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 0940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 0940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: ffb6 0640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: ffb6 0640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: ffb6 0640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: fe00 bd24 vdot\.bf16 d11, d0, d4\[1\] + *[0-9a-f]+: fe04 0d8b vdot\.bf16 d0, d20, d11\[0\] + *[0-9a-f]+: fc4a 4c40 vmmla\.bf16 q10, q5, q0 + *[0-9a-f]+: fc00 ac64 vmmla\.bf16 q5, q0, q10 + *[0-9a-f]+: fc76 48d0 vfmat\.bf16 q10, q11, q0 + *[0-9a-f]+: fe76 48f8 vfmat\.bf16 q10, q11, d0\[3\] + *[0-9a-f]+: fe76 48d0 vfmat\.bf16 q10, q11, d0\[0\] + *[0-9a-f]+: fc76 4890 vfmab\.bf16 q10, q11, q0 + *[0-9a-f]+: fe76 48b8 vfmab\.bf16 q10, q11, d0\[3\] + *[0-9a-f]+: fe76 4890 vfmab\.bf16 q10, q11, d0\[0\] + *[0-9a-f]+: fff6 464a vcvt\.bf16\.f32 d20, q5 + *[0-9a-f]+: ffb6 b664 vcvt\.bf16\.f32 d11, q10 + *[0-9a-f]+: bf18 it ne + *[0-9a-f]+: ffb6 0640 vcvtne\.bf16\.f32 d0, q0 + *[0-9a-f]+: eeb3 a965 vcvtb\.bf16\.f32 s20, s11 + *[0-9a-f]+: bf18 it ne + *[0-9a-f]+: eef3 594a vcvtbne\.bf16\.f32 s11, s20 + *[0-9a-f]+: eeb3 0940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3 a9e5 vcvtt\.bf16\.f32 s20, s11 + *[0-9a-f]+: bf18 it ne + *[0-9a-f]+: eef3 59ca vcvttne\.bf16\.f32 s11, s20 + *[0-9a-f]+: eeb3 09c0 vcvtt\.bf16\.f32 s0, s0 diff --git a/gas/testsuite/gas/arm/bfloat16-vfp.d b/gas/testsuite/gas/arm/bfloat16-vfp.d new file mode 100644 index 0000000..487aa88 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16-vfp.d @@ -0,0 +1,16 @@ +#name: Bfloat 16 VFP +#source: bfloat16-non-neon.s +#as: -mno-warn-deprecated -mfpu=vfpxd -march=armv8.6-a -I$srcdir/$subdir +#objdump: -dr --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: + +00000000 <.text>: + *[0-9a-f]*: eeb3a965 vcvtb.bf16.f32 s20, s11 + *[0-9a-f]*: 1ef3594a vcvtbne.bf16.f32 s11, s20 + *[0-9a-f]*: eeb30940 vcvtb.bf16.f32 s0, s0 + *[0-9a-f]*: eeb3a9e5 vcvtt.bf16.f32 s20, s11 + *[0-9a-f]*: 1ef359ca vcvttne.bf16.f32 s11, s20 + *[0-9a-f]*: eeb309c0 vcvtt.bf16.f32 s0, s0 diff --git a/gas/testsuite/gas/arm/bfloat16.d b/gas/testsuite/gas/arm/bfloat16.d new file mode 100644 index 0000000..b76c17f --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16.d @@ -0,0 +1,39 @@ +#name: Bfloat 16 extension +#source: bfloat16.s +#as: -mno-warn-deprecated -march=armv8.6-a+simd -I$srcdir/$subdir +#objdump: -dr --show-raw-insn + +.*: file format .* + +Disassembly of section \.text: + +00000000 <.text>: + *[0-9a-f]+: fc040d8b vdot\.bf16 d0, d20, d11 + *[0-9a-f]+: fc00bd24 vdot\.bf16 d11, d0, d20 + *[0-9a-f]+: eeb309c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb309c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb309c0 vcvtt\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb30940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb30940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb30940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: f3b60640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: f3b60640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: f3b60640 vcvt\.bf16\.f32 d0, q0 + *[0-9a-f]+: fe00bd24 vdot\.bf16 d11, d0, d4\[1\] + *[0-9a-f]+: fe040d8b vdot\.bf16 d0, d20, d11\[0\] + *[0-9a-f]+: fc4a4c40 vmmla\.bf16 q10, q5, q0 + *[0-9a-f]+: fc00ac64 vmmla\.bf16 q5, q0, q10 + *[0-9a-f]*: fc7648d0 vfmat\.bf16 q10, q11, q0 + *[0-9a-f]*: fe7648f8 vfmat\.bf16 q10, q11, d0\[3\] + *[0-9a-f]*: fe7648d0 vfmat\.bf16 q10, q11, d0\[0\] + *[0-9a-f]*: fc764890 vfmab\.bf16 q10, q11, q0 + *[0-9a-f]*: fe7648b8 vfmab\.bf16 q10, q11, d0\[3\] + *[0-9a-f]*: fe764890 vfmab\.bf16 q10, q11, d0\[0\] + *[0-9a-f]+: f3f6464a vcvt\.bf16\.f32 d20, q5 + *[0-9a-f]+: f3b6b664 vcvt\.bf16\.f32 d11, q10 + *[0-9a-f]+: eeb3a965 vcvtb\.bf16\.f32 s20, s11 + *[0-9a-f]+: 1ef3594a vcvtbne\.bf16\.f32 s11, s20 + *[0-9a-f]+: eeb30940 vcvtb\.bf16\.f32 s0, s0 + *[0-9a-f]+: eeb3a9e5 vcvtt\.bf16\.f32 s20, s11 + *[0-9a-f]+: 1ef359ca vcvttne\.bf16\.f32 s11, s20 + *[0-9a-f]+: eeb309c0 vcvtt\.bf16\.f32 s0, s0 diff --git a/gas/testsuite/gas/arm/bfloat16.s b/gas/testsuite/gas/arm/bfloat16.s new file mode 100644 index 0000000..6016ed2 --- /dev/null +++ b/gas/testsuite/gas/arm/bfloat16.s @@ -0,0 +1,2 @@ +.include "bfloat16-neon.s" +.include "bfloat16-non-neon.s" |