diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zfa-zvfh.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zfa-zvfh.s | 10 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
5 files changed, 43 insertions, 1 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 6b34c2f..e9852ef 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -2463,6 +2463,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZFH_AND_ZFA: return riscv_subset_supports (rps, "zfh") && riscv_subset_supports (rps, "zfa"); + case INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA: + return (riscv_subset_supports (rps, "zfh") + || riscv_subset_supports (rps, "zvfh")) + && riscv_subset_supports (rps, "zfa"); case INSN_CLASS_ZBA: return riscv_subset_supports (rps, "zba"); case INSN_CLASS_ZBB: @@ -2704,6 +2708,17 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zfh"; else return "zfa"; + case INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA: + if (!riscv_subset_supports (rps, "zfa")) + { + if (!riscv_subset_supports (rps, "zfh") + && !riscv_subset_supports (rps, "zvfh")) + return _("zfh' and `zfa', or `zvfh' and `zfa"); + else + return "zfa"; + } + else + return _("zfh' or `zvfh"); case INSN_CLASS_ZBA: return "zba"; case INSN_CLASS_ZBB: diff --git a/gas/testsuite/gas/riscv/zfa-zvfh.d b/gas/testsuite/gas/riscv/zfa-zvfh.d new file mode 100644 index 0000000..8fbe06c --- /dev/null +++ b/gas/testsuite/gas/riscv/zfa-zvfh.d @@ -0,0 +1,16 @@ +#as: -march=rv32iq_zfa_zvfh +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+f41c00d3[ ]+fli\.h[ ]+ft1,0x1p\+3 +[ ]+[0-9a-f]+:[ ]+f41c80d3[ ]+fli\.h[ ]+ft1,0x1p\+4 +[ ]+[0-9a-f]+:[ ]+f41d00d3[ ]+fli\.h[ ]+ft1,0x1p\+7 +[ ]+[0-9a-f]+:[ ]+f41d80d3[ ]+fli\.h[ ]+ft1,0x1p\+8 +[ ]+[0-9a-f]+:[ ]+f41e00d3[ ]+fli\.h[ ]+ft1,0x1p\+15 +[ ]+[0-9a-f]+:[ ]+f41e80d3[ ]+fli\.h[ ]+ft1,0x1p\+16 +[ ]+[0-9a-f]+:[ ]+f41f00d3[ ]+fli\.h[ ]+ft1,inf +[ ]+[0-9a-f]+:[ ]+f41f80d3[ ]+fli\.h[ ]+ft1,nan diff --git a/gas/testsuite/gas/riscv/zfa-zvfh.s b/gas/testsuite/gas/riscv/zfa-zvfh.s new file mode 100644 index 0000000..61c26e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfa-zvfh.s @@ -0,0 +1,10 @@ +target: + # fli.h is available on (('Zfh' || 'Zvfh') && 'Zfa') + fli.h ft1, 8.0 + fli.h ft1, 0x1p4 + fli.h ft1, 128.0 + fli.h ft1, 0x1p8 + fli.h ft1, 32768.0 + fli.h ft1, 0x1p16 + fli.h ft1, inf + fli.h ft1, nan diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 0b8fde9..38927bd 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -409,6 +409,7 @@ enum riscv_insn_class INSN_CLASS_D_AND_ZFA, INSN_CLASS_Q_AND_ZFA, INSN_CLASS_ZFH_AND_ZFA, + INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, INSN_CLASS_ZBA, INSN_CLASS_ZBB, INSN_CLASS_ZBC, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 02f993d..067e9fd 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -990,7 +990,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 }, {"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 }, {"fli.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Wfv", MATCH_FLI_Q, MASK_FLI_Q, match_opcode, 0 }, -{"fli.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Wfv", MATCH_FLI_H, MASK_FLI_H, match_opcode, 0 }, +{"fli.h", 0, INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, "D,Wfv", MATCH_FLI_H, MASK_FLI_H, match_opcode, 0 }, {"fminm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMINM_S, MASK_FMINM_S, match_opcode, 0 }, {"fmaxm.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMAXM_S, MASK_FMAXM_S, match_opcode, 0 }, {"fminm.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMINM_D, MASK_FMINM_D, match_opcode, 0 }, |