diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 12 | ||||
| -rw-r--r-- | gas/NEWS | 3 | ||||
| -rw-r--r-- | gas/doc/c-riscv.texi | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.s | 0 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
7 files changed, 26 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c9acf12..e2c3ffe 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1373,6 +1373,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1984,6 +1985,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension")); no_conflict = false; } + if (riscv_lookup_subset (rps->subset_list, "xtheadvector", &subset) + && riscv_lookup_subset (rps->subset_list, "v", &subset)) + { + rps->error_handler + (_("`xtheadvector' is conflict with the `v' extension")); + no_conflict = false; + } bool support_zve = false; bool support_zvl = false; @@ -2580,6 +2588,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); + case INSN_CLASS_XTHEADVECTOR: + return riscv_subset_supports (rps, "xtheadvector"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2824,6 +2834,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadmempair"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; + case INSN_CLASS_XTHEADVECTOR: + return "xtheadvector"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -31,6 +31,9 @@ * Add support for Cortex-X4 for AArch64. +* Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg + and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. + Changes in 2.41: * Add support for the KVX instruction set. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b235046..a7c9420 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -814,6 +814,11 @@ The XTheadSync extension provides instructions for multi-processor synchronizati It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadVector +The XTheadVector extension provides instructions for thead vector. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.d b/gas/testsuite/gas/riscv/x-thead-vector-fail.d new file mode 100644 index 0000000..ac99c3f --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64gcv_xtheadvector +#source: x-thead-vector.s +#error_output: x-thead-vector-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.l b/gas/testsuite/gas/riscv/x-thead-vector-fail.l new file mode 100644 index 0000000..7dd88e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.l @@ -0,0 +1,2 @@ +Assembler messages: +Error: `xtheadvector' is conflict with the `v' extension
\ No newline at end of file diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector.s diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 710a9b7..a26ef8a 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -467,6 +467,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + INSN_CLASS_XTHEADVECTOR, INSN_CLASS_XVENTANACONDOPS, }; |