gdb: riscv: enable sim integration

Now the simulator can be loaded via gdb using "target sim".

2 files changed, 76 insertions, 0 deletions

diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog
index e55363d..9eaffee 100644
--- a/sim/riscv/ChangeLog
+++ b/sim/riscv/ChangeLog
@@ -1,5 +1,11 @@
 2021-02-04  Mike Frysinger  <vapier@gentoo.org>
 
+	* sim-main.c: Include gdb/sim-riscv.h.
+	(reg_fetch, reg_store): Define.
+	(initialize_cpu): Assign reg_fetch & reg_store.
+
+2021-02-04  Mike Frysinger  <vapier@gentoo.org>
+
 	* Makefile.in, configure.ac, interp.c, machs.c, machs.h,
 	model_list.def, sim-main.c, sim-main.h: New files.
 	* aclocal.m4, config.in, configure: Regenerated.
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 323b7d9..8185bfc 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -31,6 +31,8 @@
 
 #include "opcode/riscv.h"
 
+#include "gdb/sim-riscv.h"
+
 #include "targ-vals.h"
 
 #define TRACE_REG(cpu, reg) \
@@ -1019,6 +1021,72 @@ pc_set (sim_cpu *cpu, sim_cia pc)
   cpu->pc = pc;
 }
 
+static int
+reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, int len)
+{
+  if (len <= 0 || len > sizeof (unsigned_word))
+    return -1;
+
+  switch (rn)
+    {
+    case SIM_RISCV_ZERO_REGNUM:
+      memset (buf, 0, len);
+      return len;
+    case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
+      memcpy (buf, &cpu->regs[rn], len);
+      return len;
+    case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
+      memcpy (buf, &cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], len);
+      return len;
+    case SIM_RISCV_PC_REGNUM:
+      memcpy (buf, &cpu->pc, len);
+      return len;
+
+#define DECLARE_CSR(name, num, ...) \
+    case SIM_RISCV_ ## num ## _REGNUM: \
+      memcpy (buf, &cpu->csr.name, len); \
+      return len;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+
+    default:
+      return -1;
+    }
+}
+
+static int
+reg_store (sim_cpu *cpu, int rn, unsigned char *buf, int len)
+{
+  if (len <= 0 || len > sizeof (unsigned_word))
+    return -1;
+
+  switch (rn)
+    {
+    case SIM_RISCV_ZERO_REGNUM:
+      /* Ignore writes.  */
+      return len;
+    case SIM_RISCV_RA_REGNUM ... SIM_RISCV_T6_REGNUM:
+      memcpy (&cpu->regs[rn], buf, len);
+      return len;
+    case SIM_RISCV_FIRST_FP_REGNUM ... SIM_RISCV_LAST_FP_REGNUM:
+      memcpy (&cpu->fpregs[rn - SIM_RISCV_FIRST_FP_REGNUM], buf, len);
+      return len;
+    case SIM_RISCV_PC_REGNUM:
+      memcpy (&cpu->pc, buf, len);
+      return len;
+
+#define DECLARE_CSR(name, num, ...) \
+    case SIM_RISCV_ ## num ## _REGNUM: \
+      memcpy (&cpu->csr.name, buf, len); \
+      return len;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+
+    default:
+      return -1;
+    }
+}
+
 /* Initialize the state for a single cpu.  Usuaully this involves clearing all
    registers back to their reset state.  Should also hook up the fetch/store
    helper functions too.  */
@@ -1032,6 +1100,8 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
 
   CPU_PC_FETCH (cpu) = pc_get;
   CPU_PC_STORE (cpu) = pc_set;
+  CPU_REG_FETCH (cpu) = reg_fetch;
+  CPU_REG_STORE (cpu) = reg_store;
 
   if (!riscv_hash[0])
     {