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| author | Andrew Cagney <cagney@redhat.com> | 1998-03-25 14:52:44 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-03-25 14:52:44 +0000 |
| commit | c357e16ac87e43577379e3b5bd324004aaea6725 (patch) | |
| tree | f5e5781f7b5ce604e6e7a4f0138ac02a37639e3c /sim | |
| parent | 8077fed51e73e376a74755c3fd3128a0b57b48c2 (diff) | |
| download | gdb-c357e16ac87e43577379e3b5bd324004aaea6725.zip gdb-c357e16ac87e43577379e3b5bd324004aaea6725.tar.gz gdb-c357e16ac87e43577379e3b5bd324004aaea6725.tar.bz2 | |
* dv-mn103int.c (decode_group): A group register every 4 bytes not 8.
(write_icr): Rewrite equation updating request field.
(read_iagr): Fix check that interrupt is still pending.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mn10300/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 0f66349..700ca36 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,10 @@ +Thu Mar 26 00:21:32 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * dv-mn103int.c (decode_group): A group register every 4 bytes not + 8. + (write_icr): Rewrite equation updating request field. + (read_iagr): Fix check that interrupt is still pending. + Wed Mar 25 16:14:50 1998 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (sim_open): Tidy up device creation. |