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| author | Jeff Law <jeffreyalaw@gmail.com> | 2022-04-06 11:06:53 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2022-04-06 11:06:53 -0400 |
| commit | 49fffa58f7e6da777d10fe77663bc7c8f531fe7f (patch) | |
| tree | 9b2efafe99b733a62bffb45b61c965a7a80979cc /sim/testsuite | |
| parent | 7fb56b98937a2feef5a3e12d8b00506ff4d132be (diff) | |
| download | gdb-49fffa58f7e6da777d10fe77663bc7c8f531fe7f.zip gdb-49fffa58f7e6da777d10fe77663bc7c8f531fe7f.tar.gz gdb-49fffa58f7e6da777d10fe77663bc7c8f531fe7f.tar.bz2 | |
Fix "bins" simulation for v850e3v5
I've been carrying this for a few years. One test in the GCC testsuite is
failing due to a bug in the handling of the v850e3v5 instruction "bins".
When the "bins" instruction specifies a 32bit bitfield size, the simulator
exhibits undefined behavior by trying to shift a 32 bit quantity by 32 bits.
In the case of a 32 bit shift, we know what the resultant mask should be. So
we can just set it.
That seemed better than using 1UL for the constant (on a 32bit host unsigned
long might still just be 32 bits) or needlessly forcing everything to
long long types.
Thankfully the case where this shows up is only bins <src>, 0, 32, <dest>
which would normally be encoded as a simple move.
* testsuite/v850/allinsns.exp: Add v850e3v5.
* testsuite/v850/bins.cgs: New test.
* v850/simops.c (v850_bins): Avoid undefined behavior on left shift.
Diffstat (limited to 'sim/testsuite')
| -rw-r--r-- | sim/testsuite/v850/allinsns.exp | 2 | ||||
| -rw-r--r-- | sim/testsuite/v850/bins.cgs | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/sim/testsuite/v850/allinsns.exp b/sim/testsuite/v850/allinsns.exp index 4cc461c..ee22a5d 100644 --- a/sim/testsuite/v850/allinsns.exp +++ b/sim/testsuite/v850/allinsns.exp @@ -5,7 +5,7 @@ sim_init # All machines. # Should add more cpus if the testsuite adds coverage for their insns, but # at the core level, there's no deviation beyond these two. -set all_machs "v850e v850" +set all_machs "v850e3v5 v850e v850" # gas doesn't support any '=' option for v850. set cpu_option_sep "" diff --git a/sim/testsuite/v850/bins.cgs b/sim/testsuite/v850/bins.cgs new file mode 100644 index 0000000..dedc5ce --- /dev/null +++ b/sim/testsuite/v850/bins.cgs @@ -0,0 +1,12 @@ +# v850 bins +# mach: v850e3v5 +# as: -mv850e3v5 + + .include "testutils.inc" + + seti 0x7fff, r10 + seti 0x0, r11 + bins r10, 0, 32, r11 + reg r11, 0x7fff + + pass |