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| author | Mike Frysinger <vapier@gentoo.org> | 2023-12-21 20:13:56 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2023-12-22 23:29:19 -0500 |
| commit | f0fcc327e33341648b7cec9526e1cbd2489b5330 (patch) | |
| tree | fbf9ed39041077ce15d8e8527c424639f846983b /sim/riscv | |
| parent | 5cc45e23842a4a4b7561ffe841a572969b2cc10a (diff) | |
| download | gdb-f0fcc327e33341648b7cec9526e1cbd2489b5330.zip gdb-f0fcc327e33341648b7cec9526e1cbd2489b5330.tar.gz gdb-f0fcc327e33341648b7cec9526e1cbd2489b5330.tar.bz2 | |
sim: riscv: fix -Wshadow=local warnings
Inline the one usage of sd in these macros to avoid possible shadowing.
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 4d20534..b04d12c 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -48,10 +48,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; do { \ if (RISCV_XLEN (cpu) != 32) \ { \ - SIM_DESC sd = CPU_STATE (cpu); \ TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \ - sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \ - SIM_SIGILL); \ + sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \ + sim_signalled, SIM_SIGILL); \ } \ } while (0) @@ -59,10 +58,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; do { \ if (RISCV_XLEN (cpu) != 64) \ { \ - SIM_DESC sd = CPU_STATE (cpu); \ TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \ - sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \ - SIM_SIGILL); \ + sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \ + sim_signalled, SIM_SIGILL); \ } \ } while (0) |