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authorPeter Bergner <bergner@linux.ibm.com>2021-01-08 16:07:12 -0600
committerAlan Modra <amodra@gmail.com>2021-01-09 15:16:13 +1030
commitaae7fcb8d755a2eb3f32a3f945a4e8f30cf5c5e2 (patch)
tree42165a09c958a6884c90a9126b87c3c9b3b4358a /opcodes
parent6430704567c6c3f838ad7d01d5dfcf3fcb8d6b24 (diff)
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POWER10: Add Return-Oriented Programming instructions
POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/ppc-opc.c46
2 files changed, 51 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 205c0ad..6b48181 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2021-01-08 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (insert_dw, (extract_dw): New functions.
+ (DW, (XRC_MASK): Define.
+ (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
+
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index dcff562..bbbadff 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -558,6 +558,34 @@ extract_dcmxs (uint64_t insn,
return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
}
+/* The DW field in a X form instruction when the field is split
+ into separate D and DX fields. */
+
+static uint64_t
+insert_dw (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ /* DW offsets must be in the range [-512, -8] and be a multiple of 8. */
+ if (value < -512
+ || value > -8
+ || (value & 0x7) != 0)
+ *errmsg = _("invalid offset: must be in the range [-512, -8] "
+ "and be a multiple of 8");
+
+ return insn | ((value & 0xf8) << 18) | ((value >> 8) & 1);
+}
+
+static int64_t
+extract_dw (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ int64_t dw = ((insn & 1) << 8) | ((insn >> 18) & 0xf8);
+ return dw - 512;
+}
+
/* The D field in a DX form instruction when the field is split
into separate D0, D1 and D2 fields. */
@@ -2497,8 +2525,13 @@ const struct powerpc_operand powerpc_operands[] =
#define BHRBE DUIS
{ 0x3ff, 11, NULL, NULL, 0 },
+ /* The split DW field in a X form instruction. */
+#define DW DUIS + 1
+ { -1, PPC_OPSHIFT_INV, insert_dw, extract_dw,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED},
+
/* The split D field in a DX form instruction. */
-#define DXD DUIS + 1
+#define DXD DW + 1
{ 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
@@ -3750,6 +3783,9 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
/* The mask for an X form instruction with the BF bits specified. */
#define XBF_MASK (X_MASK | (3 << 21))
+/* An X form instruction without the RC field specified. */
+#define XRC_MASK XRC (0x3f, 0x3ff, 0)
+
/* An X form wait instruction with everything filled in except the WC
field. */
#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
@@ -7656,6 +7692,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+{"hashstp", X(31,658), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
+
{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
@@ -7685,6 +7723,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
+{"hashchkp", X(31,690), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
+
{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
@@ -7715,6 +7755,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
+{"hashst", X(31,722), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
+
{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
@@ -7761,6 +7803,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
+{"hashchk", X(31,754), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
+
{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},