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authorNelson Chu <nelson.chu@sifive.com>2020-12-02 17:18:35 +0800
committerNelson Chu <nelson.chu@sifive.com>2020-12-10 10:37:43 +0800
commit729a53530e86972d1143553a415db34e6e01d5d2 (patch)
treee8a27c9d6d7f0cd468a089616450dca0ef0e7e4e /opcodes
parentcd6b05c1b2321cafe3ad9335aaa734a28f2a058e (diff)
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RISC-V: Control fence.i and csr instructions by zifencei and zicsr.
bfd/ * elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return TRUE if we don't care the versions of the extensions. These extensions are added to the subset list for special purposes, with the explicit versions or the RISCV_UNKNOWN_VERSION versions. (riscv_parse_add_subset): If we do care the versions of the extension, and the versions are unknown, then report errors for the non-implicit extensions, and return directly for the implicit one. (riscv_arch_str1): Do not output i extension after e, and the extensions which versions are unknown. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. * testsuite/gas/riscv/march-imply-i.s: New testcase. * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version of i is less than 2.1, and zi* are supported in the chosen spec, so enable the fence.i and csr instructions, also output the implicit zi* to the arch string. * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are not supported in the spec 2.2. Enable the related instructions since i's version is less than 2.1, but do not output them. * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version of i is 2.1, so don't add it's implicit zi*, and disable the related instructions. * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise. * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi* explicitly, so enable the related instructions. * testsuite/gas/riscv/march-imply-i2p0.d: Removed. * testsuite/gas/riscv/march-imply-i2p1.d: Removed. include/ * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. opcodes/ * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by zifencei and zicsr.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/riscv-opc.c40
2 files changed, 25 insertions, 20 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4ea3d76..b0cc885 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-12-10 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
+ zifencei and zicsr.
+
2020-12-04 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Add risbgz and risbgnz.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7ca44dc..4d9ba36 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -345,7 +345,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
-{"fence.i", 0, INSN_CLASS_I, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
{"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
{"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
@@ -749,25 +749,25 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
/* Supervisor instructions */
-{"csrr", 0, INSN_CLASS_I, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },
-{"csrwi", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrsi", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrci", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrw", 0, INSN_CLASS_I, "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrw", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrs", 0, INSN_CLASS_I, "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrs", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrc", 0, INSN_CLASS_I, "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrc", 0, INSN_CLASS_I, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
-{"csrrwi", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
-{"csrrsi", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
-{"csrrci", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
-{"csrrw", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
-{"csrrw", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS },
-{"csrrs", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
-{"csrrs", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS },
-{"csrrc", 0, INSN_CLASS_I, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
-{"csrrc", 0, INSN_CLASS_I, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS },
+{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },
+{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrsi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrci", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrw", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrs", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrs", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrc", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrc", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, INSN_ALIAS },
+{"csrrwi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
+{"csrrsi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
+{"csrrci", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
+{"csrrw", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
+{"csrrw", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS },
+{"csrrs", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
+{"csrrs", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS },
+{"csrrc", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
+{"csrrc", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS },
{"uret", 0, INSN_CLASS_I, "", MATCH_URET, MASK_URET, match_opcode, 0 },
{"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 },
{"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 },