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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:30:22 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-09 11:37:32 +0000 |
| commit | 4a3e3e228280ebbd6320743c1bc2f1401e70300c (patch) | |
| tree | 4391c846aaa942245299b96494f203edbe6d5d1f /opcodes | |
| parent | 8edca81ece5df534c1cdd1f8362e7b5b9b090cfa (diff) | |
| download | gdb-4a3e3e228280ebbd6320743c1bc2f1401e70300c.zip gdb-4a3e3e228280ebbd6320743c1bc2f1401e70300c.tar.gz gdb-4a3e3e228280ebbd6320743c1bc2f1401e70300c.tar.bz2 | |
aarch64: Update LS64 feature with system register
This patch:
+ Adds new ACCDATA_EL1 (Accelerator Data) system register, see [0].
+ Adds LS64 instruction tests.
+ Update LS64 feature test with new register.
+ Fix comment for AARCH64_OPND_Rt_LS64.
[0] https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/accdata_el1
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c90438c..34b2b62 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * aarch64-opc.c: Add ACCDATA_EL1 system register + +2020-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64 print. * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 67429e9..0a01de7 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4680,6 +4680,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ), SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ), + SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; |