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authorAndrew Waterman <andrew@sifive.com>2016-12-20 14:25:39 -0800
committerAlan Modra <amodra@gmail.com>2016-12-22 00:27:09 +1030
commite5b737de4a22c3099345f2613c106623d7f8d7e7 (patch)
treea8e3e35473256747bc8cb54796b94184f5bb97e3 /opcodes
parentad5bc88245bd8416fd16a2384eb00ec501bcc5e4 (diff)
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Support aligning text section from odd addresses
Previously, the alignment directives were not correctly supported in the text section when current alignment was only 1 byte (i.e., when the address was odd). Since there are no 1-byte instructions in RISC-V, this patch resolves the bug by writing a zero byte to obtain 2-byte alignment, at which point a 2-byte NOP can be used to obtain 4-byte alignment. Resolves https://github.com/riscv/riscv-gnu-toolchain/issues/205 * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs. (riscv_frag_align_code): Correct frag_align_code arg.
Diffstat (limited to 'opcodes')
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