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authorMaciej W. Rozycki <macro@imgtec.com>2016-12-20 01:50:24 +0000
committerMaciej W. Rozycki <macro@imgtec.com>2016-12-20 11:49:44 +0000
commitc97dda72b905d5ba9b82004bf4e57dd4cf343147 (patch)
tree3cfc9d566a46332f58d85bf8f4aba1692f67dae3 /opcodes
parent95f6ac8822ecbad5530c4488ac54fd46b4c658a2 (diff)
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MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/mips16-opc.c2
2 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 34486c6..4d5fae6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+ than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
+ opcode).
+
2016-12-20 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 3c90147..14d82bf 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -322,7 +322,7 @@ const struct mips_opcode mips16_opcodes[] =
{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 },
-{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
+{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 },
{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },