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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-14 21:18:16 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-14 22:04:39 +0000 |
| commit | 353abf7c10561aab3e8e7ffce6e270c3743376f0 (patch) | |
| tree | 8c3e3381198a36dacbb46cd30ce3c774e7cc803b /opcodes | |
| parent | 63e014fccdd91a89873554f6b33d7128d7112813 (diff) | |
| download | gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.zip gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.tar.gz gdb-353abf7c10561aab3e8e7ffce6e270c3743376f0.tar.bz2 | |
MIPS16: Fix SP-relative SD instruction annotation
Fix the annotation of SP-relative SD instructions incorrectly marked as
reading from the PC rather than SP, which in turn prevented their 16-bit
forms from being scheduled into jump delay slots. This bug has been
there since forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
`pinfo2' with SP-relative "sd" entries.
gas/
* testsuite/gas/mips/mips16-sprel-swap.d: New test.
* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips16-opc.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ed5764b..0138a9e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2016-12-14 Maciej W. Rozycki <macro@imgtec.com> + * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in + `pinfo2' with SP-relative "sd" entries. + +2016-12-14 Maciej W. Rozycki <macro@imgtec.com> + * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e compact jumps. diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 0fcefc6..3c90147 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -321,8 +321,8 @@ const struct mips_opcode mips16_opcodes[] = {"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, {"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, -{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_PC, I3, 0, 0 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_PC, I1, 0, 0 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 }, {"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, {"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, |