Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.

bfd/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* archures.c (bfd_mach_i386_intel_syntax): New.
	(bfd_mach_i386_i8086): Updated.
	(bfd_mach_i386_i386): Likewise.
	(bfd_mach_x86_64): Likewise.
	(bfd_mach_x64_32): Likewise.
	(bfd_mach_i386_i386_intel_syntax): Likewise.
	(bfd_mach_x86_64_intel_syntax): Likewise.
	(bfd_mach_x64_32_intel_syntax): Likewise.
	(bfd_mach_l1om): Likewise.
	(bfd_mach_l1om_intel_syntax): Likewise.
	(bfd_mach_k1om): Likewise.
	(bfd_mach_k1om_intel_syntax): Likewise.

	* bfd-in2.h: Regenerated.

	* cpu-i386.c (bfd_i386_compatible): Check mach instead of
	bits_per_address.
	(bfd_x64_32_arch_intel_syntax): Set bits_per_address to 64.
	(bfd_x64_32_arch): Likewise.

	* elf64-x86-64.c: Include "libiberty.h".
	(x86_64_elf_howto_table): Append x32 R_X86_64_32.
	(elf_x86_64_rtype_to_howto): Support x32 R_X86_64_32.
	(elf_x86_64_reloc_type_lookup): Likewise.
	(elf_x86_64_reloc_name_lookup): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_check_relocs): Allow R_X86_64_64 relocations for x32.

gas/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* config/tc-i386.c (handle_quad): Removed.
	(md_pseudo_table): Remove "quad".
	(tc_gen_reloc): Don't check BFD_RELOC_64 for disallow_64bit_reloc.
	(x86_dwarf2_addr_size): New.

	* config/tc-i386.h (x86_dwarf2_addr_size): New.
	(DWARF2_ADDR_SIZE): Likewise.

gas/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* gas/i386/ilp32/ilp32.exp: Don't run inval.

	* gas/i386/ilp32/inval.l: Removed.
	* gas/i386/ilp32/inval.s: Likewise.

	* gas/i386/ilp32/quad.d: Expect R_X86_64_64 instead of
	R_X86_64_32.

	* gas/i386/ilp32/x86-64-pcrel.s: Add tests for movabs.
	* gas/i386/ilp32/x86-64-pcrel.d: Updated.

ld/testsuite/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* ld-x86-64/ilp32-6.d: New.
	* ld-x86-64/ilp32-6.s: Likewise.
	* ld-x86-64/ilp32-7.d: Likewise.
	* ld-x86-64/ilp32-7.s: Likewise.
	* ld-x86-64/ilp32-8.d: Likewise.
	* ld-x86-64/ilp32-8.s: Likewise.
	* ld-x86-64/ilp32-9.d: Likewise.
	* ld-x86-64/ilp32-9.s: Likewise.

	* ld-x86-64/x86-64.exp: Run ilp32-6, ilp32-7, ilp32-8 and ilp32-9.

opcodes/

2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	PR ld/13048
	* i386-dis.c (print_insn): Optimize info->mach check.

2 files changed, 16 insertions, 33 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4e39050..a535831 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR ld/13048
+	* i386-dis.c (print_insn): Optimize info->mach check.
+
+2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
 	PR gas/13046
 	* i386-opc.tbl: Add Disp32S to 64bit call.
 	* i386-tbl.h: Regenerated.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 8420f55..6b5ccf2 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11161,40 +11161,19 @@ print_insn (bfd_vma pc, disassemble_info *info)
   int prefix_length;
   int default_prefixes;
 
-  if (info->mach == bfd_mach_x86_64_intel_syntax
-      || info->mach == bfd_mach_x86_64
-      || info->mach == bfd_mach_x64_32_intel_syntax
-      || info->mach == bfd_mach_x64_32
-      || info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_l1om_intel_syntax
-      || info->mach == bfd_mach_k1om
-      || info->mach == bfd_mach_k1om_intel_syntax)
-    address_mode = mode_64bit;
-  else
+  priv.orig_sizeflag = AFLAG | DFLAG;
+  if ((info->mach & bfd_mach_i386_i386) != 0)
     address_mode = mode_32bit;
-
-  if (intel_syntax == (char) -1)
-    intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
-		    || info->mach == bfd_mach_x86_64_intel_syntax
-		    || info->mach == bfd_mach_x64_32_intel_syntax
-		    || info->mach == bfd_mach_l1om_intel_syntax
-		    || info->mach == bfd_mach_k1om_intel_syntax);
-
-  if (info->mach == bfd_mach_i386_i386
-      || info->mach == bfd_mach_x86_64
-      || info->mach == bfd_mach_x64_32
-      || info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_k1om
-      || info->mach == bfd_mach_i386_i386_intel_syntax
-      || info->mach == bfd_mach_x86_64_intel_syntax
-      || info->mach == bfd_mach_x64_32_intel_syntax
-      || info->mach == bfd_mach_l1om_intel_syntax
-      || info->mach == bfd_mach_k1om_intel_syntax)
-    priv.orig_sizeflag = AFLAG | DFLAG;
   else if (info->mach == bfd_mach_i386_i8086)
-    priv.orig_sizeflag = 0;
+    {
+      address_mode = mode_16bit;
+      priv.orig_sizeflag = 0;
+    }
   else
-    abort ();
+    address_mode = mode_64bit;
+
+  if (intel_syntax == (char) -1)
+    intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
 
   for (p = info->disassembler_options; p != NULL; )
     {
@@ -11299,8 +11278,7 @@ print_insn (bfd_vma pc, disassemble_info *info)
   /* The output looks better if we put 7 bytes on a line, since that
      puts most long word instructions on a single line.  Use 8 bytes
      for Intel L1OM.  */
-  if (info->mach == bfd_mach_l1om
-      || info->mach == bfd_mach_l1om_intel_syntax)
+  if ((info->mach & bfd_mach_l1om) != 0)
     info->bytes_per_line = 8;
   else
     info->bytes_per_line = 7;