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| author | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2011-05-24 16:13:31 +0000 |
|---|---|---|
| committer | Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | 2011-05-24 16:13:31 +0000 |
| commit | c8fa16ed5ab3fe171ad9d5f5e4bad585ce639c27 (patch) | |
| tree | 8c2cfbc316f82a3ec295374d87b63e997fe8d9dc /opcodes | |
| parent | cdac0397bf4a5390c5fd087edb0bb07ce4b423ef (diff) | |
| download | gdb-c8fa16ed5ab3fe171ad9d5f5e4bad585ce639c27.zip gdb-c8fa16ed5ab3fe171ad9d5f5e4bad585ce639c27.tar.gz gdb-c8fa16ed5ab3fe171ad9d5f5e4bad585ce639c27.tar.bz2 | |
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/tc-s390.c (md_gather_operands): Fix check for floating
register pair operands.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
* s390-opc.txt: Fix cxr instruction type.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/esa-g5.d: Fix fp register pair operands.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/zarch-z196.d: Likewise.
* gas/s390/zarch-z196.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z9-ec.d: Likewise.
* gas/s390/zarch-z9-ec.s: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/s390-opc.c | 30 | ||||
| -rw-r--r-- | opcodes/s390-opc.txt | 2 |
3 files changed, 22 insertions, 16 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9fd9b23..48acc966 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + * s390-opc.c: Replace S390_OPERAND_REG_EVEN with + S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. + * s390-opc.txt: Fix cxr instruction type. + +2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + * s390-opc.c: Add new instruction types marking register pair operands. * s390-opc.txt: Match instructions having register pair operands diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 8b544cf..282298b 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -67,19 +67,19 @@ const struct s390_operand s390_operands[] = /* General purpose register pair operands. */ #define RE_8 10 /* GPR starting at position 8 */ - { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_12 11 /* GPR starting at position 12 */ - { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_16 12 /* GPR starting at position 16 */ - { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_20 13 /* GPR starting at position 20 */ - { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_24 14 /* GPR starting at position 24 */ - { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_28 15 /* GPR starting at position 28 */ - { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_32 16 /* GPR starting at position 32 */ - { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, /* Floating point register operands. */ @@ -102,19 +102,19 @@ const struct s390_operand s390_operands[] = /* Floating point register pair operands. */ #define FE_8 24 /* FPR starting at position 8 */ - { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_12 25 /* FPR starting at position 12 */ - { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_16 26 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_20 27 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_24 28 /* FPR starting at position 24 */ - { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_28 29 /* FPR starting at position 28 */ - { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_32 30 /* FPR starting at position 32 */ - { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, /* Access register operands. */ @@ -336,7 +336,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ -#define INSTR_RRF_0UFEF 4, { F_24,FE_28,U4_20,0,0,0 } /* e.g. lxdtr */ +#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index e612ca1..be44e90 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -551,7 +551,7 @@ e30000000090 llgc RXE_RRRD "load logical character" z900 zarch e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch -b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch +b369 cxr RRE_FEFE "compare extended hfp" g5 esa,zarch b3b6 cxfr RRE_FER "convert from fixed 32 to extended hfp" g5 esa,zarch b3b5 cdfr RRE_FR "convert from fixed 32 to long hfp" g5 esa,zarch b3b4 cefr RRE_FR "convert from fixed 32 to short hfp" g5 esa,zarch |