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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:20:50 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:20:50 +0000 |
| commit | 8f1bfdb44894423680a6d56a0994dafb4b82efca (patch) | |
| tree | 5bc29477c14c990a403f4711253df982b8315632 /opcodes | |
| parent | 3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38 (diff) | |
| download | gdb-8f1bfdb44894423680a6d56a0994dafb4b82efca.zip gdb-8f1bfdb44894423680a6d56a0994dafb4b82efca.tar.gz gdb-8f1bfdb44894423680a6d56a0994dafb4b82efca.tar.bz2 | |
aarch64: [SME] Add new SME system registers
This patch is adding miscellaneous SME related system registers.
gas/ChangeLog:
* testsuite/gas/aarch64/sme-sysreg.d: New test.
* testsuite/gas/aarch64/sme-sysreg.s: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.d: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.l: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.s: New test.
opcodes/ChangeLog:
* aarch64-opc.c: New system registers id_aa64smfr0_el1,
smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1,
smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-opc.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index dba8bcb..923ddef 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4826,7 +4826,17 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0), SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0), - SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0), + SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0), + SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5), F_REG_READ), + SR_SME ("smcr_el1", CPENC (3,0,C1,C2,6), 0), + SR_SME ("smcr_el12", CPENC (3,5,C1,C2,6), 0), + SR_SME ("smcr_el2", CPENC (3,4,C1,C2,6), 0), + SR_SME ("smcr_el3", CPENC (3,6,C1,C2,6), 0), + SR_SME ("smpri_el1", CPENC (3,0,C1,C2,4), 0), + SR_SME ("smprimap_el2", CPENC (3,4,C1,C2,5), 0), + SR_SME ("smidr_el1", CPENC (3,1,C0,C0,6), F_REG_READ), + SR_SME ("tpidr2_el0", CPENC (3,3,C13,C0,5), 0), + SR_SME ("mpamsm_el1", CPENC (3,0,C10,C5,3), 0), { 0, CPENC (0,0,0,0,0), 0, 0 } }; |