aarch64: Limit Rt register number for LS64 load/store instructions

Atomic 64-byte load/store instructions limit Rt register number to
values matching below condition (register <Xt> number must be even
and <= 22):

    if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED;

This patch adds check if Rt fulfills above requirement.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i

6 files changed, 183 insertions, 168 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fb6c79e..c90438c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+	* aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
+	print.
+	* aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
+	Rt_ls64 operands.
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+
 2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
 	* aarch64-tbl.h (PAC): Handle for PAC feature.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 407f893..b977115 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -625,11 +625,11 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 10:
     case 11:
     case 12:
-    case 16:
+    case 13:
     case 17:
     case 18:
     case 19:
-    case 21:
+    case 20:
     case 22:
     case 23:
     case 24:
@@ -639,7 +639,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 28:
     case 29:
     case 30:
-    case 165:
+    case 31:
     case 166:
     case 167:
     case 168:
@@ -649,7 +649,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 172:
     case 173:
     case 174:
-    case 189:
+    case 175:
     case 190:
     case 191:
     case 192:
@@ -658,34 +658,34 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 195:
     case 196:
     case 197:
-    case 203:
-    case 206:
+    case 198:
+    case 204:
+    case 207:
       return aarch64_ins_regno (self, info, code, inst, errors);
-    case 14:
-      return aarch64_ins_reg_extended (self, info, code, inst, errors);
     case 15:
+      return aarch64_ins_reg_extended (self, info, code, inst, errors);
+    case 16:
       return aarch64_ins_reg_shifted (self, info, code, inst, errors);
-    case 20:
+    case 21:
       return aarch64_ins_ft (self, info, code, inst, errors);
-    case 31:
     case 32:
     case 33:
     case 34:
-    case 209:
-      return aarch64_ins_reglane (self, info, code, inst, errors);
     case 35:
-      return aarch64_ins_reglist (self, info, code, inst, errors);
+    case 210:
+      return aarch64_ins_reglane (self, info, code, inst, errors);
     case 36:
-      return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
+      return aarch64_ins_reglist (self, info, code, inst, errors);
     case 37:
-      return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
+      return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
     case 38:
-      return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
+      return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
     case 39:
+      return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
     case 40:
     case 41:
     case 42:
-    case 52:
+    case 43:
     case 53:
     case 54:
     case 55:
@@ -702,13 +702,13 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 66:
     case 67:
     case 68:
-    case 80:
+    case 69:
     case 81:
     case 82:
     case 83:
-    case 162:
-    case 164:
-    case 181:
+    case 84:
+    case 163:
+    case 165:
     case 182:
     case 183:
     case 184:
@@ -716,96 +716,96 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 186:
     case 187:
     case 188:
-    case 208:
+    case 189:
+    case 209:
       return aarch64_ins_imm (self, info, code, inst, errors);
-    case 43:
     case 44:
-      return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
     case 45:
+      return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
     case 46:
     case 47:
+    case 48:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
-    case 51:
-    case 152:
+    case 52:
+    case 153:
       return aarch64_ins_fpimm (self, info, code, inst, errors);
-    case 69:
-    case 160:
-      return aarch64_ins_limm (self, info, code, inst, errors);
     case 70:
-      return aarch64_ins_aimm (self, info, code, inst, errors);
+    case 161:
+      return aarch64_ins_limm (self, info, code, inst, errors);
     case 71:
-      return aarch64_ins_imm_half (self, info, code, inst, errors);
+      return aarch64_ins_aimm (self, info, code, inst, errors);
     case 72:
+      return aarch64_ins_imm_half (self, info, code, inst, errors);
+    case 73:
       return aarch64_ins_fbits (self, info, code, inst, errors);
-    case 74:
     case 75:
-    case 157:
-      return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 76:
-    case 156:
     case 158:
-      return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
+      return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 77:
+    case 157:
+    case 159:
+      return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
     case 78:
+    case 79:
       return aarch64_ins_cond (self, info, code, inst, errors);
-    case 84:
-    case 93:
-      return aarch64_ins_addr_simple (self, info, code, inst, errors);
     case 85:
-      return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+    case 94:
+      return aarch64_ins_addr_simple (self, info, code, inst, errors);
     case 86:
+      return aarch64_ins_addr_regoff (self, info, code, inst, errors);
     case 87:
     case 88:
-    case 90:
-    case 92:
-      return aarch64_ins_addr_simm (self, info, code, inst, errors);
     case 89:
-      return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
     case 91:
+    case 93:
+      return aarch64_ins_addr_simm (self, info, code, inst, errors);
+    case 90:
+      return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+    case 92:
       return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
-    case 94:
-      return aarch64_ins_addr_offset (self, info, code, inst, errors);
     case 95:
-      return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
+      return aarch64_ins_addr_offset (self, info, code, inst, errors);
     case 96:
-      return aarch64_ins_sysreg (self, info, code, inst, errors);
+      return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
     case 97:
-      return aarch64_ins_pstatefield (self, info, code, inst, errors);
+      return aarch64_ins_sysreg (self, info, code, inst, errors);
     case 98:
+      return aarch64_ins_pstatefield (self, info, code, inst, errors);
     case 99:
     case 100:
     case 101:
     case 102:
-      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 103:
-    case 105:
-      return aarch64_ins_barrier (self, info, code, inst, errors);
+      return aarch64_ins_sysins_op (self, info, code, inst, errors);
     case 104:
-      return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
     case 106:
-      return aarch64_ins_prfop (self, info, code, inst, errors);
+      return aarch64_ins_barrier (self, info, code, inst, errors);
+    case 105:
+      return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
     case 107:
-      return aarch64_ins_none (self, info, code, inst, errors);
+      return aarch64_ins_prfop (self, info, code, inst, errors);
     case 108:
-      return aarch64_ins_hint (self, info, code, inst, errors);
+      return aarch64_ins_none (self, info, code, inst, errors);
     case 109:
+      return aarch64_ins_hint (self, info, code, inst, errors);
     case 110:
-      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 111:
+      return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 112:
     case 113:
     case 114:
-      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 115:
-      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 116:
-      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
     case 117:
+      return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
     case 118:
     case 119:
     case 120:
-      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 121:
+      return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 122:
     case 123:
     case 124:
@@ -819,8 +819,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 132:
     case 133:
     case 134:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 135:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 136:
     case 137:
     case 138:
@@ -828,52 +828,53 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 140:
     case 141:
     case 142:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 143:
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 144:
     case 145:
     case 146:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 147:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 148:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 149:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 150:
-      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 151:
+      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+    case 152:
       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-    case 153:
-      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 154:
-      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 155:
+      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+    case 156:
       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-    case 159:
+    case 160:
       return aarch64_ins_inv_limm (self, info, code, inst, errors);
-    case 161:
+    case 162:
       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
-    case 163:
+    case 164:
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
-    case 175:
     case 176:
     case 177:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 178:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 179:
     case 180:
+    case 181:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 198:
     case 199:
     case 200:
     case 201:
     case 202:
+    case 203:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 204:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 205:
-    case 207:
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 206:
+    case 208:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ba5cf84..f9fa3a6 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -23816,14 +23816,14 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 6:
     case 7:
     case 8:
-    case 10:
+    case 9:
     case 11:
     case 12:
-    case 16:
+    case 13:
     case 17:
     case 18:
     case 19:
-    case 21:
+    case 20:
     case 22:
     case 23:
     case 24:
@@ -23833,7 +23833,7 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 28:
     case 29:
     case 30:
-    case 165:
+    case 31:
     case 166:
     case 167:
     case 168:
@@ -23843,7 +23843,7 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 172:
     case 173:
     case 174:
-    case 189:
+    case 175:
     case 190:
     case 191:
     case 192:
@@ -23852,38 +23852,38 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 195:
     case 196:
     case 197:
-    case 203:
-    case 206:
+    case 198:
+    case 204:
+    case 207:
       return aarch64_ext_regno (self, info, code, inst, errors);
-    case 9:
+    case 10:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
-    case 13:
-      return aarch64_ext_regno_pair (self, info, code, inst, errors);
     case 14:
-      return aarch64_ext_reg_extended (self, info, code, inst, errors);
+      return aarch64_ext_regno_pair (self, info, code, inst, errors);
     case 15:
+      return aarch64_ext_reg_extended (self, info, code, inst, errors);
+    case 16:
       return aarch64_ext_reg_shifted (self, info, code, inst, errors);
-    case 20:
+    case 21:
       return aarch64_ext_ft (self, info, code, inst, errors);
-    case 31:
     case 32:
     case 33:
     case 34:
-    case 209:
-      return aarch64_ext_reglane (self, info, code, inst, errors);
     case 35:
-      return aarch64_ext_reglist (self, info, code, inst, errors);
+    case 210:
+      return aarch64_ext_reglane (self, info, code, inst, errors);
     case 36:
-      return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
+      return aarch64_ext_reglist (self, info, code, inst, errors);
     case 37:
-      return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
+      return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
     case 38:
-      return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
+      return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
     case 39:
+      return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
     case 40:
     case 41:
     case 42:
-    case 52:
+    case 43:
     case 53:
     case 54:
     case 55:
@@ -23900,14 +23900,14 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 66:
     case 67:
     case 68:
-    case 79:
+    case 69:
     case 80:
     case 81:
     case 82:
     case 83:
-    case 162:
-    case 164:
-    case 181:
+    case 84:
+    case 163:
+    case 165:
     case 182:
     case 183:
     case 184:
@@ -23915,98 +23915,98 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 186:
     case 187:
     case 188:
-    case 208:
+    case 189:
+    case 209:
       return aarch64_ext_imm (self, info, code, inst, errors);
-    case 43:
     case 44:
-      return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
     case 45:
+      return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
     case 46:
     case 47:
-      return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
     case 48:
+      return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
+    case 49:
       return aarch64_ext_shll_imm (self, info, code, inst, errors);
-    case 51:
-    case 152:
+    case 52:
+    case 153:
       return aarch64_ext_fpimm (self, info, code, inst, errors);
-    case 69:
-    case 160:
-      return aarch64_ext_limm (self, info, code, inst, errors);
     case 70:
-      return aarch64_ext_aimm (self, info, code, inst, errors);
+    case 161:
+      return aarch64_ext_limm (self, info, code, inst, errors);
     case 71:
-      return aarch64_ext_imm_half (self, info, code, inst, errors);
+      return aarch64_ext_aimm (self, info, code, inst, errors);
     case 72:
+      return aarch64_ext_imm_half (self, info, code, inst, errors);
+    case 73:
       return aarch64_ext_fbits (self, info, code, inst, errors);
-    case 74:
     case 75:
-    case 157:
-      return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
     case 76:
-    case 156:
     case 158:
-      return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
+      return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
     case 77:
+    case 157:
+    case 159:
+      return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
     case 78:
+    case 79:
       return aarch64_ext_cond (self, info, code, inst, errors);
-    case 84:
-    case 93:
-      return aarch64_ext_addr_simple (self, info, code, inst, errors);
     case 85:
-      return aarch64_ext_addr_regoff (self, info, code, inst, errors);
+    case 94:
+      return aarch64_ext_addr_simple (self, info, code, inst, errors);
     case 86:
+      return aarch64_ext_addr_regoff (self, info, code, inst, errors);
     case 87:
     case 88:
-    case 90:
-    case 92:
-      return aarch64_ext_addr_simm (self, info, code, inst, errors);
     case 89:
-      return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
     case 91:
+    case 93:
+      return aarch64_ext_addr_simm (self, info, code, inst, errors);
+    case 90:
+      return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
+    case 92:
       return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
-    case 94:
-      return aarch64_ext_addr_offset (self, info, code, inst, errors);
     case 95:
-      return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
+      return aarch64_ext_addr_offset (self, info, code, inst, errors);
     case 96:
-      return aarch64_ext_sysreg (self, info, code, inst, errors);
+      return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
     case 97:
-      return aarch64_ext_pstatefield (self, info, code, inst, errors);
+      return aarch64_ext_sysreg (self, info, code, inst, errors);
     case 98:
+      return aarch64_ext_pstatefield (self, info, code, inst, errors);
     case 99:
     case 100:
     case 101:
     case 102:
-      return aarch64_ext_sysins_op (self, info, code, inst, errors);
     case 103:
-    case 105:
-      return aarch64_ext_barrier (self, info, code, inst, errors);
+      return aarch64_ext_sysins_op (self, info, code, inst, errors);
     case 104:
-      return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
     case 106:
-      return aarch64_ext_prfop (self, info, code, inst, errors);
+      return aarch64_ext_barrier (self, info, code, inst, errors);
+    case 105:
+      return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
     case 107:
-      return aarch64_ext_none (self, info, code, inst, errors);
+      return aarch64_ext_prfop (self, info, code, inst, errors);
     case 108:
-      return aarch64_ext_hint (self, info, code, inst, errors);
+      return aarch64_ext_none (self, info, code, inst, errors);
     case 109:
+      return aarch64_ext_hint (self, info, code, inst, errors);
     case 110:
-      return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 111:
+      return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
     case 112:
     case 113:
     case 114:
-      return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 115:
-      return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
     case 116:
-      return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
     case 117:
+      return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
     case 118:
     case 119:
     case 120:
-      return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 121:
+      return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
     case 122:
     case 123:
     case 124:
@@ -24020,8 +24020,8 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 132:
     case 133:
     case 134:
-      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 135:
+      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 136:
     case 137:
     case 138:
@@ -24029,52 +24029,53 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 140:
     case 141:
     case 142:
-      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 143:
+      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 144:
     case 145:
     case 146:
-      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 147:
-      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 148:
-      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 149:
-      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 150:
-      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 151:
+      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+    case 152:
       return aarch64_ext_sve_asimm (self, info, code, inst, errors);
-    case 153:
-      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 154:
-      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 155:
+      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+    case 156:
       return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
-    case 159:
+    case 160:
       return aarch64_ext_inv_limm (self, info, code, inst, errors);
-    case 161:
+    case 162:
       return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
-    case 163:
+    case 164:
       return aarch64_ext_sve_scale (self, info, code, inst, errors);
-    case 175:
     case 176:
     case 177:
-      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 178:
+      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 179:
     case 180:
+    case 181:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 198:
     case 199:
     case 200:
     case 201:
     case 202:
+    case 203:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 204:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 205:
-    case 207:
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 206:
+    case 208:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index e3d47b4..f5c6709 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -30,6 +30,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 3f14287..67429e9 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3174,6 +3174,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_Rt2:
     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
+    case AARCH64_OPND_Rt_LS64:
     case AARCH64_OPND_Rt_SYS:
     case AARCH64_OPND_PAIRREG:
     case AARCH64_OPND_SVE_Rm:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f86dde5..a54b968 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3646,10 +3646,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19),    QL_X_PCREL, 0),
   CORE_INSN ("prfm",  0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT,  OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0),
   /* Atomic 64-byte load/store in Armv8.7.  */
-  _LS64_INSN ("ld64b",   0xf83fd000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
-  _LS64_INSN ("st64b",   0xf83f9000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
-  _LS64_INSN ("st64bv",  0xf820b000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0),
-  _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LS64_INSN ("ld64b",   0xf83fd000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0),
+  _LS64_INSN ("st64b",   0xf83f9000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0),
+  _LS64_INSN ("st64bv",  0xf820b000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
   /* Logical (immediate).  */
   CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
   CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF),
@@ -5181,6 +5181,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register")	\
     Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register")	\
     Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register")	\
+    Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register")	\
     Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt),		\
       "an integer or stack pointer register")				\
     Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register")	\