bpf: xBPF SDIV, SMOD instructions

Add gas and opcodes support for two xBPF-exclusive ALU operations:
SDIV (signed division) and SMOD (signed modulo), and add tests for
them in gas.

cpu/
	* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
	(define-alu-insn-bin, daib): Take ISAs as an argument.
	(define-alu-instructions): Update calls to daib pmacro with
	ISAs; add sdiv and smod.

gas/
	* testsuite/gas/bpf/alu-xbpf.d: New file.
	* testsuite/gas/bpf/alu-xbpf.s: Likewise.
	* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
	* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
	* testuiste/gas/bpf/bpf.exp: Run new tests.

opcodes/
	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

5 files changed, 194 insertions, 6 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6243511..0f3c270 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-09-18  David Faust  <david.faust@oracle.com>
+
+	* bpf-desc.c: Regenerate.
+	* bpf-desc.h: Likewise.
+	* bpf-opc.c: Likewise.
+	* bpf-opc.h: Likewise.
+
 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 
 	* csky-dis.c (csky_get_disassembler): Don't return NULL when there
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
index 6914ce9..adcff34 100644
--- a/opcodes/bpf-desc.c
+++ b/opcodes/bpf-desc.c
@@ -520,6 +520,46 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
     BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
+/* sdiv $dstle,$imm32 */
+  {
+    BPF_INSN_SDIVILE, "sdivile", "sdiv", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* sdiv $dstle,$srcle */
+  {
+    BPF_INSN_SDIVRLE, "sdivrle", "sdiv", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* sdiv32 $dstle,$imm32 */
+  {
+    BPF_INSN_SDIV32ILE, "sdiv32ile", "sdiv32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* sdiv32 $dstle,$srcle */
+  {
+    BPF_INSN_SDIV32RLE, "sdiv32rle", "sdiv32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* smod $dstle,$imm32 */
+  {
+    BPF_INSN_SMODILE, "smodile", "smod", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* smod $dstle,$srcle */
+  {
+    BPF_INSN_SMODRLE, "smodrle", "smod", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* smod32 $dstle,$imm32 */
+  {
+    BPF_INSN_SMOD32ILE, "smod32ile", "smod32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* smod32 $dstle,$srcle */
+  {
+    BPF_INSN_SMOD32RLE, "smod32rle", "smod32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
 /* neg $dstle */
   {
     BPF_INSN_NEGLE, "negle", "neg", 64,
@@ -770,6 +810,46 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
     BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
+/* sdiv $dstbe,$imm32 */
+  {
+    BPF_INSN_SDIVIBE, "sdivibe", "sdiv", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* sdiv $dstbe,$srcbe */
+  {
+    BPF_INSN_SDIVRBE, "sdivrbe", "sdiv", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* sdiv32 $dstbe,$imm32 */
+  {
+    BPF_INSN_SDIV32IBE, "sdiv32ibe", "sdiv32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* sdiv32 $dstbe,$srcbe */
+  {
+    BPF_INSN_SDIV32RBE, "sdiv32rbe", "sdiv32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* smod $dstbe,$imm32 */
+  {
+    BPF_INSN_SMODIBE, "smodibe", "smod", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* smod $dstbe,$srcbe */
+  {
+    BPF_INSN_SMODRBE, "smodrbe", "smod", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* smod32 $dstbe,$imm32 */
+  {
+    BPF_INSN_SMOD32IBE, "smod32ibe", "smod32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
+/* smod32 $dstbe,$srcbe */
+  {
+    BPF_INSN_SMOD32RBE, "smod32rbe", "smod32", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
+  },
 /* neg $dstbe */
   {
     BPF_INSN_NEGBE, "negbe", "neg", 64,
diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h
index dd24996..04e2af1 100644
--- a/opcodes/bpf-desc.h
+++ b/opcodes/bpf-desc.h
@@ -67,10 +67,11 @@ typedef enum insn_op_code_alu {
   OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
  , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
  , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
- , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_JA = 0, OP_CODE_JEQ = 1
- , OP_CODE_JGT = 2, OP_CODE_JGE = 3, OP_CODE_JSET = 4, OP_CODE_JNE = 5
- , OP_CODE_JSGT = 6, OP_CODE_JSGE = 7, OP_CODE_CALL = 8, OP_CODE_EXIT = 9
- , OP_CODE_JLT = 10, OP_CODE_JLE = 11, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
+ , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_SDIV = 14, OP_CODE_SMOD = 15
+ , OP_CODE_JA = 0, OP_CODE_JEQ = 1, OP_CODE_JGT = 2, OP_CODE_JGE = 3
+ , OP_CODE_JSET = 4, OP_CODE_JNE = 5, OP_CODE_JSGT = 6, OP_CODE_JSGE = 7
+ , OP_CODE_CALL = 8, OP_CODE_EXIT = 9, OP_CODE_JLT = 10, OP_CODE_JLE = 11
+ , OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
 } INSN_OP_CODE_ALU;
 
 /* Enum declaration for eBPF instruction source.  */
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 72d5cd2..5a157ee 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -424,6 +424,54 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
     & ifmt_addrle, { 0xcc }
   },
+/* sdiv $dstle,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+    & ifmt_addile, { 0xe7 }
+  },
+/* sdiv $dstle,$srcle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+    & ifmt_addrle, { 0xef }
+  },
+/* sdiv32 $dstle,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+    & ifmt_addile, { 0xe4 }
+  },
+/* sdiv32 $dstle,$srcle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+    & ifmt_addrle, { 0xec }
+  },
+/* smod $dstle,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+    & ifmt_addile, { 0xf7 }
+  },
+/* smod $dstle,$srcle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+    & ifmt_addrle, { 0xff }
+  },
+/* smod32 $dstle,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+    & ifmt_addile, { 0xf4 }
+  },
+/* smod32 $dstle,$srcle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+    & ifmt_addrle, { 0xfc }
+  },
 /* neg $dstle */
   {
     { 0, 0, 0, 0 },
@@ -724,6 +772,54 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
     & ifmt_addrbe, { 0xcc }
   },
+/* sdiv $dstbe,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+    & ifmt_addibe, { 0xe7 }
+  },
+/* sdiv $dstbe,$srcbe */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+    & ifmt_addrbe, { 0xef }
+  },
+/* sdiv32 $dstbe,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+    & ifmt_addibe, { 0xe4 }
+  },
+/* sdiv32 $dstbe,$srcbe */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+    & ifmt_addrbe, { 0xec }
+  },
+/* smod $dstbe,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+    & ifmt_addibe, { 0xf7 }
+  },
+/* smod $dstbe,$srcbe */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+    & ifmt_addrbe, { 0xff }
+  },
+/* smod32 $dstbe,$imm32 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+    & ifmt_addibe, { 0xf4 }
+  },
+/* smod32 $dstbe,$srcbe */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+    & ifmt_addrbe, { 0xfc }
+  },
 /* neg $dstbe */
   {
     { 0, 0, 0, 0 },
diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
index 5d5150c..c3f9362 100644
--- a/opcodes/bpf-opc.h
+++ b/opcodes/bpf-opc.h
@@ -59,7 +59,9 @@ typedef enum cgen_insn_type {
  , BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
  , BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
  , BPF_INSN_XOR32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
- , BPF_INSN_ARSH32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
+ , BPF_INSN_ARSH32RLE, BPF_INSN_SDIVILE, BPF_INSN_SDIVRLE, BPF_INSN_SDIV32ILE
+ , BPF_INSN_SDIV32RLE, BPF_INSN_SMODILE, BPF_INSN_SMODRLE, BPF_INSN_SMOD32ILE
+ , BPF_INSN_SMOD32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
  , BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE, BPF_INSN_MOV32RLE, BPF_INSN_ADDIBE
  , BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
  , BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
@@ -71,7 +73,9 @@ typedef enum cgen_insn_type {
  , BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
  , BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
  , BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_ARSHIBE
- , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_NEGBE
+ , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_SDIVIBE
+ , BPF_INSN_SDIVRBE, BPF_INSN_SDIV32IBE, BPF_INSN_SDIV32RBE, BPF_INSN_SMODIBE
+ , BPF_INSN_SMODRBE, BPF_INSN_SMOD32IBE, BPF_INSN_SMOD32RBE, BPF_INSN_NEGBE
  , BPF_INSN_NEG32BE, BPF_INSN_MOVIBE, BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE
  , BPF_INSN_MOV32RBE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
  , BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW