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authorNick Clifton <nickc@redhat.com>2000-12-01 20:05:32 +0000
committerNick Clifton <nickc@redhat.com>2000-12-01 20:05:32 +0000
commit4372b673222291cc81879e291c0233c6cc08a4d3 (patch)
tree25e1fe72333a5b5eb8a0cd24724df167adb9ba02 /opcodes
parent0c92ba5f58ea1b2c2ee6401419899883b726b39e (diff)
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Improve MIPS32 support
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog14
-rw-r--r--opcodes/mips-dis.c38
-rw-r--r--opcodes/mips-opc.c25
3 files changed, 62 insertions, 15 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ba54c74..debb7fb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2000-12-01 Chris Demetriou <cgd@sibyte.com>
+
+ mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
+ specifiers. Update 'B' for new constant names, and remove
+ 'm'.
+ mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
+ near the top of the array, so they are disassembled properly.
+ Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
+ code for MIPS32. Update "clo" and "clz" to use 'U' operand
+ specifier. Add 'H' format specifier variants for "mfc1,"
+ "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
+ MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
+ "wait" variant which uses 'J' operand specifier.
+
2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 4c76cde..39bcf33 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -157,6 +157,30 @@ print_insn_arg (d, l, pc, info)
reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
+ case 'U':
+ {
+ /* First check for both rd and rt being equal. */
+ int reg = (l >> OP_SH_RD) & OP_MASK_RD;
+ if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else
+ {
+ /* If one is zero use the other. */
+ if (reg == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
+ (*info->fprintf_func) (info->stream, "$%s",
+ reg_names[reg]);
+ else /* Bogus, result depends on processor. */
+ (*info->fprintf_func) (info->stream, "$%s or $%s",
+ reg_names[reg],
+ reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ }
+ }
+ break;
+
case 'z':
(*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
break;
@@ -171,17 +195,11 @@ print_insn_arg (d, l, pc, info)
(l >> OP_SH_CODE) & OP_MASK_CODE);
break;
-
case 'q':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
break;
- case 'm':
- (*info->fprintf_func) (info->stream, "0x%x",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
- break;
-
case 'C':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_COPZ) & OP_MASK_COPZ);
@@ -189,7 +207,12 @@ print_insn_arg (d, l, pc, info)
case 'B':
(*info->fprintf_func) (info->stream, "0x%x",
- (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
+ (l >> OP_SH_CODE20) & OP_MASK_CODE20);
+ break;
+
+ case 'J':
+ (*info->fprintf_func) (info->stream, "0x%x",
+ (l >> OP_SH_CODE19) & OP_MASK_CODE19);
break;
case 'S':
@@ -198,7 +221,6 @@ print_insn_arg (d, l, pc, info)
(l >> OP_SH_FS) & OP_MASK_FS);
break;
-
case 'T':
case 'W':
(*info->fprintf_func) (info->stream, "$f%d",
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 1c2a249..3e19ffa 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -107,12 +107,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
-const struct mips_opcode mips_builtin_opcodes[] = {
+const struct mips_opcode mips_builtin_opcodes[] =
+{
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
-{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
+{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4},
+{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
+{"ssnop", "", 0x00000040, 0xffffffff, 0, M1|P4 },
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
@@ -220,6 +223,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
+{"break", "B", 0x0000000d, 0xfc00003f, TRAP, P4 },
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
@@ -328,8 +332,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
-{"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d|RD_s, P4 },
-{"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d|RD_s, P4 },
+{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, P4 },
+{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, P4 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
@@ -545,8 +549,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
+{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, P4},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
+{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
@@ -580,8 +587,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
+{"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, P4 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, P4 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
+{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, P4 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
@@ -620,7 +630,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
-{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 },
+/* pref is at the start of the table. */
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
@@ -657,7 +667,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
-{"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP, P4 },
+{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, P4 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
@@ -711,7 +721,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
-{"ssnop", "", 0x00000040, 0xffffffff, 0, M1 },
+/* ssnop is at the start of the table. */
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
@@ -810,6 +820,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 },
+{"wait", "J", 0x42000020, 0xfe00003f, TRAP, P4 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
/* No hazard protection on coprocessor instructions--they shouldn't