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| author | Graham Markall <graham.markall@embecosm.com> | 2016-06-01 16:29:27 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2016-06-01 16:29:27 +0100 |
| commit | 315f180f2f0a59af561180e4ed9387f4c7bada78 (patch) | |
| tree | 0a1c4e6394085a1974446cacfe860363020ec902 /opcodes | |
| parent | 51403f74d96cc69f391fbd31389a9153a230b431 (diff) | |
| download | gdb-315f180f2f0a59af561180e4ed9387f4c7bada78.zip gdb-315f180f2f0a59af561180e4ed9387f4c7bada78.tar.gz gdb-315f180f2f0a59af561180e4ed9387f4c7bada78.tar.bz2 | |
Add support for some variants of the ARC nps400 rflt instruction.
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
0,b,limm to the rflt instruction.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arc-nps400-tbl.h | 19 |
2 files changed, 19 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c1023ad..c636013 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-06-01 Graham Markall <graham.markall@embecosm.com> + + * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and + 0,b,limm to the rflt instruction. + 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 5716119..c7019a9 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -40,21 +40,30 @@ /* rflt a,limm,c 0011111000101110F111CCCCCCAAAAAA */ { "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { 0 }}, +/* rflt a,b,u6 00111bbb01101110FBBBuuuuuuAAAAAA */ +{ "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, + /* rflt 0,b,c 00111bbb00101110FBBBCCCCCC111110 */ { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { 0 }}, /* rflt 0,limm,c 0011111000101110F111CCCCCC111110 */ { "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { 0 }}, -/* rflt a,b,u6 00111bbb01101110FBBBuuuuuuAAAAAA */ -{ "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, +/* rflt 0,b,u6 00111bbb01101110FBBBuuuuuu111110 */ +{ "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, + +/* rflt 0,b,limm 00111bbb00101110FBBB111110111110 */ +{ "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* rflt a,b,limm 00111bbb00101110FBBB111110AAAAAA */ +{ "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* rflt a,limm,limm 0011111000101110F111111110AAAAAA */ +{ "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, /* rflt a,limm,u6 0011111001101110F111uuuuuuAAAAAA */ { "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, -/* rflt 0,b,u6 00111bbb01101110FBBBuuuuuu111110 */ -{ "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, - /* rflt 0,limm,u6 0011111001101110F111uuuuuu111110 */ { "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }}, |