Add support for ARMv8-M security extensions instructions

2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
	shared with a non M profile architecture.
	(do_rn): New function.
	(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
	than arm_ext_v8m.
	(v7m_psrs): Add ARMv8-M security extensions new special registers.
	(insns): Add ARMv8-M Security Extensions instructions.
	(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
	arm_ext_v8m_m to decide the profile and the Thumb ISA.
	* testsuite/gas/arm/archv8m-cmse.s: New file.
	* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
	* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
	* testsuite/gas/arm/any-cmse.d: Likewise.
	* testsuite/gas/arm/any-cmse-main.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.

include/
	* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
	(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
	(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
	for the high core bits.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	Mainline Security Extensions instructions.
	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	Extensions instructions.
	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	instructions.
	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	special registers.

2 files changed, 29 insertions, 1 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3df576e..2e2aaf5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
+	Mainline Security Extensions instructions.
+	(thumb_opcodes): Add entries for narrow ARMv8-M Security
+	Extensions instructions.
+	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
+	instructions.
+	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
+	special registers.
+
 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 0fb4586..3d69c7d 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -408,6 +408,12 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 
+  /* ARMv8-M Mainline Security Extensions instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
+
   /* Register load/store.  */
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
@@ -2469,6 +2475,10 @@ static const struct opcode16 thumb_opcodes[] =
 {
   /* Thumb instructions.  */
 
+  /* ARMv8-M Security Extensions instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
+
   /* ARM V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
@@ -2674,11 +2684,16 @@ static const struct opcode16 thumb_opcodes[] =
    makes heavy use of special-case bit patterns.  */
 static const struct opcode32 thumb32_opcodes[] =
 {
-  /* V8-M instructions.  */
+  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
 
   /* ARM V8.2 RAS extension instructions.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
@@ -5426,6 +5441,8 @@ psr_name (int regno)
     case 18: return "BASEPRI_MAX";
     case 19: return "FAULTMASK";
     case 20: return "CONTROL";
+    case 0x88: return "MSP_NS";
+    case 0x89: return "PSP_NS";
     default: return "<unknown>";
     }
 }