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| author | Jan Beulich <jbeulich@novell.com> | 2017-11-15 08:48:51 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-11-15 08:48:51 +0100 |
| commit | 0645f0a2a75ad77d9786595978591d3f302f9647 (patch) | |
| tree | dbb506276f9cd08824e99995a4a471403b9d56ee /opcodes | |
| parent | 99847db8ea741f895d79b9312114c13ccb660d83 (diff) | |
| download | gdb-0645f0a2a75ad77d9786595978591d3f302f9647.zip gdb-0645f0a2a75ad77d9786595978591d3f302f9647.tar.gz gdb-0645f0a2a75ad77d9786595978591d3f302f9647.tar.bz2 | |
x86-64: don't allow use of %axl as accumulator
Just like %cxl can't be used as shift count register. Otherwise for
consistency %cxl would need to gain "ShiftCount" and use of both ought
to properly cause REX prefixes to be emitted.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-reg.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 68cbfcc..e8af8b2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-11-15 Jan Beulich <jbeulich@suse.com> + + * i386-reg.tbl (axl): Remove Acc and Byte. + * i386-tbl.h: Re-generate. + 2017-11-14 Jan Beulich <jbeulich@suse.com> * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New. diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index fa9c856..0c4e796 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -29,7 +29,7 @@ ah, Reg8, 0, 4, Dw2Inval, Dw2Inval ch, Reg8, 0, 5, Dw2Inval, Dw2Inval dh, Reg8, 0, 6, Dw2Inval, Dw2Inval bh, Reg8, 0, 7, Dw2Inval, Dw2Inval -axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 85075d6..364bc97 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -101351,7 +101351,7 @@ const reg_entry i386_regtab[] = 0, 7, { Dw2Inval, Dw2Inval } }, { "axl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "cxl", |