backout m32rx stuff, not ready to be checked in

8 files changed, 1097 insertions, 1530 deletions

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 0df3e20..0f44eb8 100644
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -87,9 +87,7 @@ hppa-dis.c
 i386-dis.c
 i960-dis.c
 m32r-asm.c
-m32r-asm.in
 m32r-dis.c
-m32r-dis.in
 m32r-opc.c
 m32r-opc.h
 m68k-dis.c
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bc1c89e..b772d4b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,22 +1,3 @@
-Thu Jan 15 10:32:06 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r-dis.c (print_insn): Only look for parallel 16 bit
-	instructions on a 32 bit boundary.
-
-Wed Jan 14 17:37:03 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r-asm.in: Generated file imported from cgen.
-	* m32r-dis.in: Generated file imported from cgen.
-	* cgen-asm.in: Formatting changes to improve readability.
-	* m32r-asm.c:  Formatting changes to improve readability.
-	* cgen-dis.c:  Formatting changes to improve readability.
-	* m32r-dis.c:  Add support for disassembling parallel
-	instructions. 
-	* m32r-opc.h:  Update with latest version generated by cgen.
-	* m32r-opc.c:  Update with latest version generated by cgen, plus
-	hand patches to allow attributes to work until cgen can generate
-	these correctly.
-	
 start-sanitize-r5900
 Tue Jan 13 09:21:56 1998  Jeffrey A Law  (law@cygnus.com)
 
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index f63c373..f8f140c 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -56,10 +56,13 @@ static void insert_insn_normal
 
 static CGEN_INLINE void
 insert_normal (value, attrs, start, length, shift, total_length, buffer)
-     long value;
+     long         value;
      unsigned int attrs;
-     int start, length, shift, total_length;
-     char *buffer;
+     int          start;
+     int          length;
+     int          shift;
+     int          total_length;
+     char *       buffer;
 {
   bfd_vma x;
 
@@ -70,7 +73,7 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
   switch (total_length)
     {
     case 8:
-      x = *(unsigned char *) buffer;
+      x = * (unsigned char *) buffer;
       break;
     case 16:
       if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
@@ -99,7 +102,7 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
   switch (total_length)
     {
     case 8:
-      *buffer = value;
+      * buffer = value;
       break;
     case 16:
       if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
@@ -120,6 +123,404 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
 }
 
 /* -- assembler routines inserted here */
+/* -- asm.c */
+
+/* Handle shigh(), high().  */
+
+static const char *
+parse_h_hi16 (strp, opindex, min, max, valuep)
+     const char **strp;
+     int opindex;
+     unsigned long min, max;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+
+  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncmp (*strp, "high(", 5) == 0)
+    {
+      *strp += 5;
+      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO,
+				   &result_type, valuep);
+      if (**strp != ')')
+	return "missing `)'";
+      ++*strp;
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	*valuep >>= 16;
+      return errmsg;
+    }
+  else if (strncmp (*strp, "shigh(", 6) == 0)
+    {
+      *strp += 6;
+      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO,
+ 				   &result_type, valuep);
+      if (**strp != ')')
+	return "missing `)'";
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	*valuep = (*valuep >> 16) + ((*valuep) & 0x8000 ? 1 : 0);
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+}
+
+/* Handle low() in a signed context.  Also handle sda().
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_h_slo16 (strp, opindex, min, max, valuep)
+     const char **strp;
+     int opindex;
+     long min, max;
+     long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+
+  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
+				   &result_type, valuep);
+      if (**strp != ')')
+	return "missing `)'";
+      ++*strp;
+      return errmsg;
+    }
+
+  if (strncmp (*strp, "sda(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, NULL, valuep);
+      if (**strp != ')')
+	return "missing `)'";
+      ++*strp;
+      return errmsg;
+    }
+
+  return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
+}
+
+/* Handle low() in an unsigned context.
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_h_ulo16 (strp, opindex, min, max, valuep)
+     const char **strp;
+     int opindex;
+     unsigned long min, max;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+
+  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
+				   &result_type, valuep);
+      if (**strp != ')')
+	return "missing `)'";
+      ++*strp;
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+}
+
+/* -- */
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.
+*/
+
+CGEN_INLINE const char *
+m32r_cgen_parse_operand (opindex, strp, fields)
+     int opindex;
+     const char ** strp;
+     CGEN_FIELDS * fields;
+{
+  const char * errmsg;
+
+  switch (opindex)
+    {
+    case M32R_OPERAND_SR :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r2);
+      break;
+    case M32R_OPERAND_DR :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r1);
+      break;
+    case M32R_OPERAND_SRC1 :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r1);
+      break;
+    case M32R_OPERAND_SRC2 :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, & fields->f_r2);
+      break;
+    case M32R_OPERAND_SCR :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r2);
+      break;
+    case M32R_OPERAND_DCR :
+      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r1);
+      break;
+    case M32R_OPERAND_SIMM8 :
+      errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8);
+      break;
+    case M32R_OPERAND_SIMM16 :
+      errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16);
+      break;
+    case M32R_OPERAND_UIMM4 :
+      errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4);
+      break;
+    case M32R_OPERAND_UIMM5 :
+      errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5);
+      break;
+    case M32R_OPERAND_UIMM16 :
+      errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
+      break;
+    case M32R_OPERAND_HI16 :
+      errmsg = parse_h_hi16 (strp, 12, 0, 65535, &fields->f_hi16);
+      break;
+    case M32R_OPERAND_SLO16 :
+      errmsg = parse_h_slo16 (strp, 13, -32768, 32767, &fields->f_simm16);
+      break;
+    case M32R_OPERAND_ULO16 :
+      errmsg = parse_h_ulo16 (strp, 14, 0, 65535, &fields->f_uimm16);
+      break;
+    case M32R_OPERAND_UIMM24 :
+      errmsg = cgen_parse_address (strp, 15, 0, NULL, & fields->f_uimm24);
+      break;
+    case M32R_OPERAND_DISP8 :
+      errmsg = cgen_parse_address (strp, 16, 0, NULL, & fields->f_disp8);
+      break;
+    case M32R_OPERAND_DISP16 :
+      errmsg = cgen_parse_address (strp, 17, 0, NULL, & fields->f_disp16);
+      break;
+    case M32R_OPERAND_DISP24 :
+      errmsg = cgen_parse_address (strp, 18, 0, NULL, & fields->f_disp24);
+      break;
+
+    default :
+      fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.
+*/
+
+CGEN_INLINE void
+m32r_cgen_insert_operand (opindex, fields, buffer)
+     int           opindex;
+     CGEN_FIELDS * fields;
+     cgen_insn_t * buffer;
+{
+  switch (opindex)
+    {
+    case M32R_OPERAND_SR :
+      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_DR :
+      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SRC1 :
+      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SRC2 :
+      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SCR :
+      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_DCR :
+      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SIMM8 :
+      insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SIMM16 :
+      insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_UIMM4 :
+      insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_UIMM5 :
+      insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_UIMM16 :
+      insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_HI16 :
+      insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_SLO16 :
+      insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_ULO16 :
+      insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_UIMM24 :
+      insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_DISP8 :
+      insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_DISP16 :
+      insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+    case M32R_OPERAND_DISP24 :
+      insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+      break;
+
+    default :
+      fprintf (stderr, "Unrecognized field %d while building insn.\n",
+	       opindex);
+      abort ();
+  }
+}
+
+/* Main entry point for operand validation.
+
+   This function is called from GAS when it has fully resolved an operand
+   that couldn't be resolved during parsing.
+
+   The result is NULL for success or an error message (which may be
+   computed into a static buffer).
+*/
+
+CGEN_INLINE const char *
+m32r_cgen_validate_operand (opindex, fields)
+     int                 opindex;
+     const CGEN_FIELDS * fields;
+{
+  const char * errmsg = NULL;
+
+  switch (opindex)
+    {
+    case M32R_OPERAND_SR :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_DR :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_SRC1 :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_SRC2 :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_SCR :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_DCR :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_SIMM8 :
+      errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
+      break;
+    case M32R_OPERAND_SIMM16 :
+      errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+      break;
+    case M32R_OPERAND_UIMM4 :
+      errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
+      break;
+    case M32R_OPERAND_UIMM5 :
+      errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
+      break;
+    case M32R_OPERAND_UIMM16 :
+      errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+      break;
+    case M32R_OPERAND_HI16 :
+      errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
+      break;
+    case M32R_OPERAND_SLO16 :
+      errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+      break;
+    case M32R_OPERAND_ULO16 :
+      errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+      break;
+    case M32R_OPERAND_UIMM24 :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_DISP8 :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_DISP16 :
+      /* nothing to do */
+      break;
+    case M32R_OPERAND_DISP24 :
+      /* nothing to do */
+      break;
+
+    default :
+      fprintf (stderr, "Unrecognized field %d while validating operand.\n",
+	       opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * m32r_cgen_parse_handlers[] = 
+{  0, /* default */
+  parse_insn_normal,
+};
+
+cgen_insert_fn * m32r_cgen_insert_handlers[] = 
+{  0, /* default */
+  insert_insn_normal,
+};
+
+void
+m32r_cgen_init_asm (mach, endian)
+     int mach;
+     enum cgen_endian endian;
+{
+  m32r_cgen_init_tables (mach);
+  cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
+  cgen_asm_init ();
+}
+
 
 /* Default insn parser.
 
@@ -137,25 +538,25 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
 
 static const char *
 parse_insn_normal (insn, strp, fields)
-     const CGEN_INSN *insn;
-     const char **strp;
-     CGEN_FIELDS *fields;
+     const CGEN_INSN *  insn;
+     const char **      strp;
+     CGEN_FIELDS *      fields;
 {
-  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
-  const char *str = *strp;
-  const char *errmsg;
-  const char *p;
-  const unsigned char *syn;
+  const CGEN_SYNTAX *   syntax = CGEN_INSN_SYNTAX (insn);
+  const char *          str = *strp;
+  const char *          errmsg;
+  const char *          p;
+  const unsigned char * syn;
 #ifdef CGEN_MNEMONIC_OPERANDS
-  int past_opcode_p;
+  int                   past_opcode_p;
 #endif
 
   /* For now we assume the mnemonic is first (there are no leading operands).
      We can parse it without needing to set up operand parsing.  */
   p = CGEN_INSN_MNEMONIC (insn);
-  while (*p && *p == *str)
-    ++p, ++str;
-  if (*p || (*str && !isspace (*str)))
+  while (* p && * p == * str)
+    ++ p, ++ str;
+  if (* p || (* str && !isspace (* str)))
     return "unrecognized instruction";
 
   CGEN_INIT_PARSE ();
@@ -167,24 +568,27 @@ parse_insn_normal (insn, strp, fields)
   /* We don't check for (*str != '\0') here because we want to parse
      any trailing fake arguments in the syntax string.  */
   syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
+  
   /* Mnemonics come first for now, ensure valid string.  */
-  if (! CGEN_SYNTAX_MNEMONIC_P (*syn))
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
     abort ();
+  
   ++syn;
-  while (*syn != 0)
+  
+  while (* syn != 0)
     {
       /* Non operand chars must match exactly.  */
       /* FIXME: Need to better handle whitespace.  */
-      if (CGEN_SYNTAX_CHAR_P (*syn))
+      if (CGEN_SYNTAX_CHAR_P (* syn))
 	{
-	  if (*str == CGEN_SYNTAX_CHAR (*syn))
+	  if (*str == CGEN_SYNTAX_CHAR (* syn))
 	    {
 #ifdef CGEN_MNEMONIC_OPERANDS
-	      if (*syn == ' ')
+	      if (* syn == ' ')
 		past_opcode_p = 1;
 #endif
-	      ++syn;
-	      ++str;
+	      ++ syn;
+	      ++ str;
 	    }
 	  else
 	    {
@@ -202,20 +606,20 @@ parse_insn_normal (insn, strp, fields)
 	return errmsg;
 
       /* Done with this operand, continue with next one.  */
-      ++syn;
+      ++ syn;
     }
 
   /* If we're at the end of the syntax string, we're done.  */
-  if (*syn == '\0')
+  if (* syn == '\0')
     {
       /* FIXME: For the moment we assume a valid `str' can only contain
 	 blanks now.  IE: We needn't try again with a longer version of
 	 the insn and it is assumed that longer versions of insns appear
 	 before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
-      while (isspace (*str))
-	++str;
+      while (isspace (* str))
+	++ str;
 
-      if (*str != '\0')
+      if (* str != '\0')
 	return "junk at end of line"; /* FIXME: would like to include `str' */
 
       return NULL;
@@ -230,13 +634,13 @@ parse_insn_normal (insn, strp, fields)
 
 static void
 insert_insn_normal (insn, fields, buffer)
-     const CGEN_INSN *insn;
-     CGEN_FIELDS *fields;
-     cgen_insn_t *buffer;
+     const CGEN_INSN *  insn;
+     CGEN_FIELDS *      fields;
+     cgen_insn_t *      buffer;
 {
-  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
-  bfd_vma value;
-  const unsigned char *syn;
+  const CGEN_SYNTAX *   syntax = CGEN_INSN_SYNTAX (insn);
+  bfd_vma               value;
+  const unsigned char * syn;
 
   CGEN_INIT_INSERT ();
   value = CGEN_INSN_VALUE (insn);
@@ -251,7 +655,7 @@ insert_insn_normal (insn, fields, buffer)
   switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields)))
     {
     case 8:
-      *buffer = value;
+      * buffer = value;
       break;
     case 16:
       if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
@@ -273,9 +677,9 @@ insert_insn_normal (insn, fields, buffer)
   /* ??? Rather than scanning the syntax string again, we could store
      in `fields' a null terminated list of the fields that are present.  */
 
-  for (syn = CGEN_SYNTAX_STRING (syntax); *syn != '\0'; ++syn)
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
     {
-      if (CGEN_SYNTAX_CHAR_P (*syn))
+      if (CGEN_SYNTAX_CHAR_P (* syn))
 	continue;
 
       m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer);
@@ -292,17 +696,17 @@ insert_insn_normal (insn, fields, buffer)
 
 const CGEN_INSN *
 m32r_cgen_assemble_insn (str, fields, buf, errmsg)
-     const char *str;
-     CGEN_FIELDS *fields;
-     cgen_insn_t *buf;
-     char **errmsg;
+     const char *  str;
+     CGEN_FIELDS * fields;
+     cgen_insn_t * buf;
+     char **       errmsg;
 {
-  const char *start;
-  CGEN_INSN_LIST *ilist;
+  const char *     start;
+  CGEN_INSN_LIST * ilist;
 
   /* Skip leading white space.  */
-  while (isspace (*str))
-    ++str;
+  while (isspace (* str))
+    ++ str;
 
   /* The instructions are stored in hashed lists.
      Get the first in the list.  */
@@ -343,9 +747,9 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg)
 	 inline functions but of course that would only work for gcc.  Since
 	 we're machine generating some code we could do that here too.  Maybe
 	 later.  */
-      if (! (*CGEN_PARSE_FN (insn)) (insn, &str, fields))
+      if (! CGEN_PARSE_FN (insn) (insn, & str, fields))
 	{
-	  (*CGEN_INSERT_FN (insn)) (insn, fields, buf);
+	  CGEN_INSERT_FN (insn) (insn, fields, buf);
 	  /* It is up to the caller to actually output the insn and any
 	     queued relocs.  */
 	  return insn;
@@ -376,12 +780,12 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg)
 
 void
 m32r_cgen_asm_hash_keywords (opvals)
-     CGEN_KEYWORD *opvals;
+     CGEN_KEYWORD * opvals;
 {
   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
-  const CGEN_KEYWORD_ENTRY *ke;
+  const CGEN_KEYWORD_ENTRY * ke;
 
-  while ((ke = cgen_keyword_search_next (&search)) != NULL)
+  while ((ke = cgen_keyword_search_next (& search)) != NULL)
     {
 #if 0 /* Unnecessary, should be done in the search routine.  */
       if (! m32r_cgen_opval_supported (ke))
diff --git a/opcodes/m32r-asm.in b/opcodes/m32r-asm.in
deleted file mode 100644
index 70f67ff..0000000
--- a/opcodes/m32r-asm.in
+++ /dev/null
@@ -1,416 +0,0 @@
-/* -- asm.c */
-
-/* Handle shigh(), high().  */
-
-static const char *
-parse_h_hi16 (strp, opindex, min, max, valuep)
-     const char **strp;
-     int opindex;
-     unsigned long min, max;
-     unsigned long *valuep;
-{
-  const char *errmsg;
-  enum cgen_parse_operand_result result_type;
-
-  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
-  if (**strp == '#')
-    ++*strp;
-
-  if (strncmp (*strp, "high(", 5) == 0)
-    {
-      *strp += 5;
-      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO,
-				   &result_type, valuep);
-      if (**strp != ')')
-	return "missing `)'";
-      ++*strp;
-      if (errmsg == NULL
-  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	*valuep >>= 16;
-      return errmsg;
-    }
-  else if (strncmp (*strp, "shigh(", 6) == 0)
-    {
-      *strp += 6;
-      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO,
- 				   &result_type, valuep);
-      if (**strp != ')')
-	return "missing `)'";
-      ++*strp;
-      if (errmsg == NULL
-	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	*valuep = (*valuep >> 16) + ((*valuep) & 0x8000 ? 1 : 0);
-      return errmsg;
-    }
-
-  return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
-}
-
-/* Handle low() in a signed context.  Also handle sda().
-   The signedness of the value doesn't matter to low(), but this also
-   handles the case where low() isn't present.  */
-
-static const char *
-parse_h_slo16 (strp, opindex, min, max, valuep)
-     const char **strp;
-     int opindex;
-     long min, max;
-     long *valuep;
-{
-  const char *errmsg;
-  enum cgen_parse_operand_result result_type;
-
-  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
-  if (**strp == '#')
-    ++*strp;
-
-  if (strncmp (*strp, "low(", 4) == 0)
-    {
-      *strp += 4;
-      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
-				   &result_type, valuep);
-      if (**strp != ')')
-	return "missing `)'";
-      ++*strp;
-      return errmsg;
-    }
-
-  if (strncmp (*strp, "sda(", 4) == 0)
-    {
-      *strp += 4;
-      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, NULL, valuep);
-      if (**strp != ')')
-	return "missing `)'";
-      ++*strp;
-      return errmsg;
-    }
-
-  return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
-}
-
-/* Handle low() in an unsigned context.
-   The signedness of the value doesn't matter to low(), but this also
-   handles the case where low() isn't present.  */
-
-static const char *
-parse_h_ulo16 (strp, opindex, min, max, valuep)
-     const char **strp;
-     int opindex;
-     unsigned long min, max;
-     unsigned long *valuep;
-{
-  const char *errmsg;
-  enum cgen_parse_operand_result result_type;
-
-  /* FIXME: Need # in assembler syntax (means '#' is optional).  */
-  if (**strp == '#')
-    ++*strp;
-
-  if (strncmp (*strp, "low(", 4) == 0)
-    {
-      *strp += 4;
-      errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
-				   &result_type, valuep);
-      if (**strp != ')')
-	return "missing `)'";
-      ++*strp;
-      return errmsg;
-    }
-
-  return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
-}
-
-/* -- */
-
-/* Main entry point for operand parsing.
-
-   This function is basically just a big switch statement.  Earlier versions
-   used tables to look up the function to use, but
-   - if the table contains both assembler and disassembler functions then
-     the disassembler contains much of the assembler and vice-versa,
-   - there's a lot of inlining possibilities as things grow,
-   - using a switch statement avoids the function call overhead.
-
-   This function could be moved into `parse_insn_normal', but keeping it
-   separate makes clear the interface between `parse_insn_normal' and each of
-   the handlers.
-*/
-
-CGEN_INLINE const char *
-m32r_cgen_parse_operand (opindex, strp, fields)
-     int opindex;
-     const char **strp;
-     CGEN_FIELDS *fields;
-{
-  const char *errmsg;
-
-  switch (opindex)
-    {
-    case M32R_OPERAND_SR :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
-      break;
-    case M32R_OPERAND_DR :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
-      break;
-    case M32R_OPERAND_SRC1 :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
-      break;
-    case M32R_OPERAND_SRC2 :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
-      break;
-    case M32R_OPERAND_SCR :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2);
-      break;
-    case M32R_OPERAND_DCR :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1);
-      break;
-    case M32R_OPERAND_SIMM8 :
-      errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8);
-      break;
-    case M32R_OPERAND_SIMM16 :
-      errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16);
-      break;
-    case M32R_OPERAND_UIMM4 :
-      errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4);
-      break;
-    case M32R_OPERAND_UIMM5 :
-      errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5);
-      break;
-    case M32R_OPERAND_UIMM16 :
-      errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
-      break;
-    case M32R_OPERAND_ACC_S :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc_s);
-      break;
-    case M32R_OPERAND_ACC :
-      errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc);
-      break;
-    case M32R_OPERAND_HI16 :
-      errmsg = parse_h_hi16 (strp, 14, 0, 65535, &fields->f_hi16);
-      break;
-    case M32R_OPERAND_SLO16 :
-      errmsg = parse_h_slo16 (strp, 15, -32768, 32767, &fields->f_simm16);
-      break;
-    case M32R_OPERAND_ULO16 :
-      errmsg = parse_h_ulo16 (strp, 16, 0, 65535, &fields->f_uimm16);
-      break;
-    case M32R_OPERAND_UIMM24 :
-      errmsg = cgen_parse_address (strp, 17, 0, NULL, &fields->f_uimm24);
-      break;
-    case M32R_OPERAND_DISP8 :
-      errmsg = cgen_parse_address (strp, 18, 0, NULL, &fields->f_disp8);
-      break;
-    case M32R_OPERAND_DISP16 :
-      errmsg = cgen_parse_address (strp, 19, 0, NULL, &fields->f_disp16);
-      break;
-    case M32R_OPERAND_DISP24 :
-      errmsg = cgen_parse_address (strp, 20, 0, NULL, &fields->f_disp24);
-      break;
-
-    default :
-      fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
-      abort ();
-  }
-
-  return errmsg;
-}
-
-/* Main entry point for operand insertion.
-
-   This function is basically just a big switch statement.  Earlier versions
-   used tables to look up the function to use, but
-   - if the table contains both assembler and disassembler functions then
-     the disassembler contains much of the assembler and vice-versa,
-   - there's a lot of inlining possibilities as things grow,
-   - using a switch statement avoids the function call overhead.
-
-   This function could be moved into `parse_insn_normal', but keeping it
-   separate makes clear the interface between `parse_insn_normal' and each of
-   the handlers.  It's also needed by GAS to insert operands that couldn't be
-   resolved during parsing.
-*/
-
-CGEN_INLINE void
-m32r_cgen_insert_operand (opindex, fields, buffer)
-     int opindex;
-     CGEN_FIELDS *fields;
-     cgen_insn_t *buffer;
-{
-  switch (opindex)
-    {
-    case M32R_OPERAND_SR :
-      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_DR :
-      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SRC1 :
-      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SRC2 :
-      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SCR :
-      insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_DCR :
-      insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SIMM8 :
-      insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SIMM16 :
-      insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_UIMM4 :
-      insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_UIMM5 :
-      insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_UIMM16 :
-      insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_ACC_S :
-      insert_normal (fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_ACC :
-      insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_HI16 :
-      insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_SLO16 :
-      insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_ULO16 :
-      insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_UIMM24 :
-      insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_DISP8 :
-      insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_DISP16 :
-      insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-    case M32R_OPERAND_DISP24 :
-      insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
-      break;
-
-    default :
-      fprintf (stderr, "Unrecognized field %d while building insn.\n",
-	       opindex);
-      abort ();
-  }
-}
-
-/* Main entry point for operand validation.
-
-   This function is called from GAS when it has fully resolved an operand
-   that couldn't be resolved during parsing.
-
-   The result is NULL for success or an error message (which may be
-   computed into a static buffer).
-*/
-
-CGEN_INLINE const char *
-m32r_cgen_validate_operand (opindex, fields)
-     int opindex;
-     const CGEN_FIELDS *fields;
-{
-  const char *errmsg = NULL;
-
-  switch (opindex)
-    {
-    case M32R_OPERAND_SR :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_DR :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_SRC1 :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_SRC2 :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_SCR :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_DCR :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_SIMM8 :
-      errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
-      break;
-    case M32R_OPERAND_SIMM16 :
-      errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
-      break;
-    case M32R_OPERAND_UIMM4 :
-      errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
-      break;
-    case M32R_OPERAND_UIMM5 :
-      errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
-      break;
-    case M32R_OPERAND_UIMM16 :
-      errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
-      break;
-    case M32R_OPERAND_ACC_S :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_ACC :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_HI16 :
-      errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
-      break;
-    case M32R_OPERAND_SLO16 :
-      errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
-      break;
-    case M32R_OPERAND_ULO16 :
-      errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
-      break;
-    case M32R_OPERAND_UIMM24 :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_DISP8 :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_DISP16 :
-      /* nothing to do */
-      break;
-    case M32R_OPERAND_DISP24 :
-      /* nothing to do */
-      break;
-
-    default :
-      fprintf (stderr, "Unrecognized field %d while validating operand.\n",
-	       opindex);
-      abort ();
-  }
-
-  return errmsg;
-}
-
-cgen_parse_fn *m32r_cgen_parse_handlers[] = {
-  0, /* default */
-  parse_insn_normal,
-};
-
-cgen_insert_fn *m32r_cgen_insert_handlers[] = {
-  0, /* default */
-  insert_insn_normal,
-};
-
-void
-m32r_cgen_init_asm (mach, endian)
-     int mach;
-     enum cgen_endian endian;
-{
-  m32r_cgen_init_tables (mach);
-  cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
-  cgen_asm_init ();
-}
-
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 05555b2..1b0a8ea 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -49,11 +49,6 @@ static int extract_insn_normal
      PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *));
 static void print_insn_normal
      PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int));
-
-CGEN_INLINE void
-m32r_cgen_print_operand
-     PARAMS ((int opindex, disassemble_info * info, CGEN_FIELDS * fields, void const * attrs, bfd_vma pc, int length));
-
 
 /* Default extraction routine.
 
@@ -62,14 +57,11 @@ m32r_cgen_print_operand
 
 static int
 extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep)
-     void *       buf_ctrl;
-     cgen_insn_t  insn_value;
+     void *buf_ctrl;
+     cgen_insn_t insn_value;
      unsigned int attrs;
-     int          start;
-     int          length;
-     int          shift;
-     int          total_length;
-     long *       valuep;
+     int start, length, shift, total_length;
+     long *valuep;
 {
   long value;
 
@@ -94,7 +86,7 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length,
   else
     value <<= shift;
 
-  * valuep = value;
+  *valuep = value;
   return 1;
 }
 
@@ -102,13 +94,13 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length,
 
 static void
 print_normal (dis_info, value, attrs, pc, length)
-     void *        dis_info;
-     long          value;
-     unsigned int  attrs;
+     void *dis_info;
+     long value;
+     unsigned int attrs;
      unsigned long pc; /* FIXME: should be bfd_vma */
-     int           length;
+     int length;
 {
-  disassemble_info * info = dis_info;
+  disassemble_info *info = dis_info;
 
   /* Print the operand as directed by the attributes.  */
   if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE))
@@ -129,19 +121,262 @@ print_normal (dis_info, value, attrs, pc, length)
 
 static void
 print_keyword (dis_info, keyword_table, value, attrs)
-     void *         dis_info;
-     CGEN_KEYWORD * keyword_table;
-     long           value;
-     CGEN_ATTR *    attrs;
+     void *dis_info;
+     CGEN_KEYWORD *keyword_table;
+     long value;
+     CGEN_ATTR *attrs;
 {
-  disassemble_info * info = dis_info;
-  const CGEN_KEYWORD_ENTRY * ke;
+  disassemble_info *info = dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
 
   ke = cgen_keyword_lookup_value (keyword_table, value);
-  info->fprintf_func (info->stream, "%s", ke == NULL ? "???" : ke->name);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    (*info->fprintf_func) (info->stream, "???");
 }
 
 /* -- disassembler routines inserted here */
+/* -- dis.c */
+
+#undef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN my_print_insn
+
+static int
+my_print_insn (pc, info, buf, buflen)
+     bfd_vma pc;
+     disassemble_info *info;
+     char *buf;
+     int buflen;
+{
+  /* 32 bit insn?  */
+  if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+    return print_insn (pc, info, buf, buflen);
+
+  /* Print the first insn.  */
+  if ((pc & 3) == 0)
+    {
+      if (print_insn (pc, info, buf, 16) == 0)
+	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+      buf += 2;
+    }
+
+  if (buf[0] & 0x80)
+    {
+      /* Parallel.  */
+      (*info->fprintf_func) (info->stream, " || ");
+      buf[0] &= 0x7f;
+    }
+  else
+    (*info->fprintf_func) (info->stream, " -> ");
+
+  /* The "& 3" is to ensure the branch address is computed correctly
+     [if it is a branch].  */
+  if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
+    (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+
+  return (pc & 3) ? 2 : 4;
+}
+
+/* -- */
+
+/* Main entry point for operand extraction.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.
+*/
+
+CGEN_INLINE int
+m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
+     int           opindex;
+     void *        buf_ctrl;
+     cgen_insn_t   insn_value;
+     CGEN_FIELDS * fields;
+{
+  int length;
+
+  switch (opindex)
+    {
+    case M32R_OPERAND_SR :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+      break;
+    case M32R_OPERAND_DR :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+      break;
+    case M32R_OPERAND_SRC1 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+      break;
+    case M32R_OPERAND_SRC2 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+      break;
+    case M32R_OPERAND_SCR :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+      break;
+    case M32R_OPERAND_DCR :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+      break;
+    case M32R_OPERAND_SIMM8 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
+      break;
+    case M32R_OPERAND_SIMM16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
+      break;
+    case M32R_OPERAND_UIMM4 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
+      break;
+    case M32R_OPERAND_UIMM5 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
+      break;
+    case M32R_OPERAND_UIMM16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
+      break;
+    case M32R_OPERAND_HI16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
+      break;
+    case M32R_OPERAND_SLO16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
+      break;
+    case M32R_OPERAND_ULO16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
+      break;
+    case M32R_OPERAND_UIMM24 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
+      break;
+    case M32R_OPERAND_DISP8 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp8);
+      break;
+    case M32R_OPERAND_DISP16 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp16);
+      break;
+    case M32R_OPERAND_DISP24 :
+      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp24);
+      break;
+
+    default :
+      fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
+	       opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+/* Main entry point for printing operands.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.
+*/
+
+CGEN_INLINE void
+m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
+     int                opindex;
+     disassemble_info * info;
+     CGEN_FIELDS *      fields;
+     void const *       attrs;
+     bfd_vma            pc;
+     int                length;
+{
+  switch (opindex)
+    {
+    case M32R_OPERAND_SR :
+      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_DR :
+      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_SRC1 :
+      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_SRC2 :
+      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_SCR :
+      print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_DCR :
+      print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case M32R_OPERAND_SIMM8 :
+      print_normal (info, fields->f_simm8, 0, pc, length);
+      break;
+    case M32R_OPERAND_SIMM16 :
+      print_normal (info, fields->f_simm16, 0, pc, length);
+      break;
+    case M32R_OPERAND_UIMM4 :
+      print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_UIMM5 :
+      print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_UIMM16 :
+      print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_HI16 :
+      print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_SLO16 :
+      print_normal (info, fields->f_simm16, 0, pc, length);
+      break;
+    case M32R_OPERAND_ULO16 :
+      print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_UIMM24 :
+      print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case M32R_OPERAND_DISP8 :
+      print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case M32R_OPERAND_DISP16 :
+      print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case M32R_OPERAND_DISP24 :
+      print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+
+    default :
+      fprintf (stderr, "Unrecognized field %d while printing insn.\n",
+	       opindex);
+    abort ();
+  }
+}
+
+cgen_extract_fn * m32r_cgen_extract_handlers[] = 
+{  0, /* default */
+  extract_insn_normal,
+};
+
+cgen_print_fn * m32r_cgen_print_handlers[] = 
+{  0, /* default */
+  print_insn_normal,
+};
+
+
+void
+m32r_cgen_init_dis (mach, endian)
+     int mach;
+     enum cgen_endian endian;
+{
+  m32r_cgen_init_tables (mach);
+  cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
+  cgen_dis_init ();
+}
+
 
 /* Default insn extractor.
 
@@ -151,26 +386,26 @@ print_keyword (dis_info, keyword_table, value, attrs)
 
 static int
 extract_insn_normal (insn, buf_ctrl, insn_value, fields)
-     const CGEN_INSN *  insn;
-     void *             buf_ctrl;
-     cgen_insn_t        insn_value;
-     CGEN_FIELDS *      fields;
+     const CGEN_INSN *insn;
+     void *buf_ctrl;
+     cgen_insn_t insn_value;
+     CGEN_FIELDS *fields;
 {
-  const CGEN_SYNTAX *   syntax = CGEN_INSN_SYNTAX (insn);
-  const unsigned char * syn;
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const unsigned char *syn;
 
   CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
 
   CGEN_INIT_EXTRACT ();
 
-  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
     {
       int length;
 
-      if (CGEN_SYNTAX_CHAR_P (* syn))
+      if (CGEN_SYNTAX_CHAR_P (*syn))
 	continue;
 
-      length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (* syn),
+      length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn),
 					   buf_ctrl, insn_value, fields);
       if (length == 0)
 	return 0;
@@ -188,33 +423,33 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields)
 
 static void
 print_insn_normal (dis_info, insn, fields, pc, length)
-     void *             dis_info;
-     const CGEN_INSN *  insn;
-     CGEN_FIELDS *      fields;
-     bfd_vma            pc;
-     int                length;
+     void *dis_info;
+     const CGEN_INSN *insn;
+     CGEN_FIELDS *fields;
+     bfd_vma pc;
+     int length;
 {
-  const CGEN_SYNTAX *   syntax = CGEN_INSN_SYNTAX (insn);
-  disassemble_info *    info = dis_info;
-  const unsigned char * syn;
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  disassemble_info *info = dis_info;
+  const unsigned char *syn;
 
   CGEN_INIT_PRINT ();
 
-  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
     {
-      if (CGEN_SYNTAX_MNEMONIC_P (* syn))
+      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 	{
-	  info->fprintf_func (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 	  continue;
 	}
-      if (CGEN_SYNTAX_CHAR_P (* syn))
+      if (CGEN_SYNTAX_CHAR_P (*syn))
 	{
-	  info->fprintf_func (info->stream, "%c", CGEN_SYNTAX_CHAR (* syn));
+	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 	  continue;
 	}
 
       /* We have an operand.  */
-      m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (* syn), info,
+      m32r_cgen_print_operand (CGEN_SYNTAX_FIELD (*syn), info,
 				fields, CGEN_INSN_ATTRS (insn), pc, length);
     }
 }
@@ -231,16 +466,15 @@ print_insn_normal (dis_info, insn, fields, pc, length)
 
 static int
 print_insn (pc, info, buf, buflen)
-     bfd_vma            pc;
-     disassemble_info * info;
-     char *             buf;
-     int                buflen;
+     bfd_vma pc;
+     disassemble_info *info;
+     char *buf;
+     int buflen;
 {
-  int                    i;
-  unsigned long          insn_value;
-  const CGEN_INSN_LIST * insn_list;
-  int                    extra_bytes;
-  
+  int i;
+  unsigned long insn_value;
+  const CGEN_INSN_LIST *insn_list;
+
   switch (buflen)
     {
     case 8:
@@ -256,53 +490,16 @@ print_insn (pc, info, buf, buflen)
       abort ();
     }
 
-  /* Special case - a 32 bit instruction which is actually two 16 bit instructions
-     being executed in parallel.  */
-  if (buflen == 32
-      && (pc & 0x3) == 0
-      && ((insn_value & 0x80008000) == 0x00008000))
-    {
-      if (info->endian == BFD_ENDIAN_BIG)
-	{
-	  static char buf2 [4];
-	  
-	  print_insn (pc, info, buf, 16);
-
-	  info->fprintf_func (info->stream, " || ");
-
-	  buf2 [0] = buf [2] & ~ 0x80;
-	  buf2 [1] = buf [3];
-	  buf2 [2] = 0;
-	  buf2 [3] = 0;
-	  buf = buf2;
-	  
-	  insn_value <<= 17;
-	  insn_value >>= 1;
-	}
-      else
-	{
-	  print_insn (pc, info, buf + 2, 16);
-
-	  info->fprintf_func (info->stream, " || ");
-
-	  insn_value &= 0x7fff;
-	}
-
-      pc += 2;
-      extra_bytes = 2;
-    }
-  else
-    extra_bytes = 0;
-  
   /* The instructions are stored in hash lists.
      Pick the first one and keep trying until we find the right one.  */
 
   insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
-
   while (insn_list != NULL)
     {
-      const CGEN_INSN *   insn = insn_list->insn;
-      unsigned long       value;
+      const CGEN_INSN *insn = insn_list->insn;
+      const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+      CGEN_FIELDS fields;
+      int length;
 
 #if 0 /* not needed as insn shouldn't be in hash lists if not supported */
       /* Supported by this cpu?  */
@@ -310,43 +507,28 @@ print_insn (pc, info, buf, buflen)
 	continue;
 #endif
 
-      /* If we are looking at a 16 bit insn we may have to adjust the value being examined.  */
-      value = insn_value;
-      if (CGEN_INSN_BITSIZE (insn) == 16)
-	{
-	/* If this is a big endian target,
-	   and we have read 32 bits for the instruction value,
-	   then we must examine the top 16 bits, not the bottom.  */
-	  if (buflen == 32 && info->endian == BFD_ENDIAN_BIG)
-	    value >>= 16;
-	}
-      
       /* Basic bit mask must be correct.  */
       /* ??? May wish to allow target to defer this check until the extract
 	 handler.  */
-      if ((value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+      if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 	{
-	  CGEN_FIELDS fields;
-	  int         length;
-	  
 	  /* Printing is handled in two passes.  The first pass parses the
 	     machine insn and extracts the fields.  The second pass prints
 	     them.  */
 
-	  length = CGEN_EXTRACT_FN (insn) (insn, NULL, value, & fields);
+	  length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields);
 	  if (length > 0)
 	    {
-	      CGEN_PRINT_FN (insn) (info, insn, & fields, pc, length);
-	      
+	      (*CGEN_PRINT_FN (insn)) (info, insn, &fields, pc, length);
 	      /* length is in bits, result is in bytes */
-	      return (length / 8) + extra_bytes;
+	      return length / 8;
 	    }
 	}
-      
+
       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
     }
 
-  return extra_bytes;
+  return 0;
 }
 
 /* Main entry point.
@@ -355,41 +537,32 @@ print_insn (pc, info, buf, buflen)
 
 int
 print_insn_m32r (pc, info)
-     bfd_vma            pc;
-     disassemble_info * info;
+     bfd_vma pc;
+     disassemble_info *info;
 {
-  char       buffer [CGEN_MAX_INSN_SIZE];
-  int        status;
-  int        length;
-  static int initialized    = 0;
-  static int current_mach   = 0;
-  static int current_bigend = 0;
-  int        mach           = info->mach;
-  int        bigend         = info->endian == BFD_ENDIAN_BIG;
+  char buffer[CGEN_MAX_INSN_SIZE];
+  int status, length;
+  static int initialized = 0;
+  static int current_mach = 0;
+  static int current_big_p = 0;
+  int mach = info->mach;
+  int big_p = info->endian == BFD_ENDIAN_BIG;
 
   /* If we haven't initialized yet, or if we've switched cpu's, initialize.  */
-  if (!initialized || mach != current_mach || bigend != current_bigend)
+  if (!initialized || mach != current_mach || big_p != current_big_p)
     {
-      initialized    = 1;
-      current_mach   = mach;
-      current_bigend = bigend;
-      
-      m32r_cgen_init_dis (mach, bigend ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
+      initialized = 1;
+      current_mach = mach;
+      current_big_p = big_p;
+      m32r_cgen_init_dis (mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
     }
 
   /* Read enough of the insn so we can look it up in the hash lists.  */
 
-  status = info->read_memory_func (pc, buffer, CGEN_BASE_INSN_SIZE, info);
+  status = (*info->read_memory_func) (pc, buffer, CGEN_BASE_INSN_SIZE, info);
   if (status != 0)
     {
-      /* Try reading a 16 bit instruction.  */
-      info->bytes_per_chunk = 2;
-      status = info->read_memory_func (pc, buffer, CGEN_BASE_INSN_SIZE / 2, info);
-      buffer [2] = buffer [3] = 0;
-    }
-  if (status != 0)
-    {
-      info->memory_error_func (status, pc, info);
+      (*info->memory_error_func) (status, pc, info);
       return -1;
     }
 
@@ -399,14 +572,9 @@ print_insn_m32r (pc, info)
      but if not possible try to move this hook elsewhere rather than
      have two hooks.  */
   length = CGEN_PRINT_INSN (pc, info, buffer, CGEN_BASE_INSN_BITSIZE);
-  
   if (length)
     return length;
 
-  info->fprintf_func (info->stream, UNKNOWN_INSN_MSG);
-  
+  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
   return CGEN_DEFAULT_INSN_SIZE;
 }
-
-/* Get the generate machine specific code.  */
-#include "m32r-dis.in"
diff --git a/opcodes/m32r-dis.in b/opcodes/m32r-dis.in
deleted file mode 100644
index 3e5fb7f..0000000
--- a/opcodes/m32r-dis.in
+++ /dev/null
@@ -1,252 +0,0 @@
-/* -- dis.c */
-
-#undef CGEN_PRINT_INSN
-#define CGEN_PRINT_INSN my_print_insn
-
-static int
-my_print_insn (pc, info, buf, buflen)
-     bfd_vma pc;
-     disassemble_info *info;
-     char *buf;
-     int buflen;
-{
-  /* 32 bit insn?  */
-  if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
-    return print_insn (pc, info, buf, buflen);
-
-  /* Print the first insn.  */
-  if ((pc & 3) == 0)
-    {
-      if (print_insn (pc, info, buf, 16) == 0)
-	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
-      buf += 2;
-    }
-
-  if (buf[0] & 0x80)
-    {
-      /* Parallel.  */
-      (*info->fprintf_func) (info->stream, " || ");
-      buf[0] &= 0x7f;
-    }
-  else
-    (*info->fprintf_func) (info->stream, " -> ");
-
-  /* The "& 3" is to ensure the branch address is computed correctly
-     [if it is a branch].  */
-  if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
-    (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
-
-  return (pc & 3) ? 2 : 4;
-}
-
-/* -- */
-
-/* Main entry point for operand extraction.
-
-   This function is basically just a big switch statement.  Earlier versions
-   used tables to look up the function to use, but
-   - if the table contains both assembler and disassembler functions then
-     the disassembler contains much of the assembler and vice-versa,
-   - there's a lot of inlining possibilities as things grow,
-   - using a switch statement avoids the function call overhead.
-
-   This function could be moved into `print_insn_normal', but keeping it
-   separate makes clear the interface between `print_insn_normal' and each of
-   the handlers.
-*/
-
-CGEN_INLINE int
-m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
-     int opindex;
-     void *buf_ctrl;
-     cgen_insn_t insn_value;
-     CGEN_FIELDS *fields;
-{
-  int length;
-
-  switch (opindex)
-    {
-    case M32R_OPERAND_SR :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
-      break;
-    case M32R_OPERAND_DR :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
-      break;
-    case M32R_OPERAND_SRC1 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
-      break;
-    case M32R_OPERAND_SRC2 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
-      break;
-    case M32R_OPERAND_SCR :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
-      break;
-    case M32R_OPERAND_DCR :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
-      break;
-    case M32R_OPERAND_SIMM8 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8);
-      break;
-    case M32R_OPERAND_SIMM16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
-      break;
-    case M32R_OPERAND_UIMM4 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm4);
-      break;
-    case M32R_OPERAND_UIMM5 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm5);
-      break;
-    case M32R_OPERAND_UIMM16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
-      break;
-    case M32R_OPERAND_ACC_S :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc_s);
-      break;
-    case M32R_OPERAND_ACC :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc);
-      break;
-    case M32R_OPERAND_HI16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_hi16);
-      break;
-    case M32R_OPERAND_SLO16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
-      break;
-    case M32R_OPERAND_ULO16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
-      break;
-    case M32R_OPERAND_UIMM24 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm24);
-      break;
-    case M32R_OPERAND_DISP8 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp8);
-      break;
-    case M32R_OPERAND_DISP16 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp16);
-      break;
-    case M32R_OPERAND_DISP24 :
-      length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp24);
-      break;
-
-    default :
-      fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
-	       opindex);
-      abort ();
-    }
-
-  return length;
-}
-
-/* Main entry point for printing operands.
-
-   This function is basically just a big switch statement.  Earlier versions
-   used tables to look up the function to use, but
-   - if the table contains both assembler and disassembler functions then
-     the disassembler contains much of the assembler and vice-versa,
-   - there's a lot of inlining possibilities as things grow,
-   - using a switch statement avoids the function call overhead.
-
-   This function could be moved into `print_insn_normal', but keeping it
-   separate makes clear the interface between `print_insn_normal' and each of
-   the handlers.
-*/
-
-CGEN_INLINE void
-m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
-     int opindex;
-     disassemble_info *info;
-     CGEN_FIELDS *fields;
-     void const * attrs;
-     bfd_vma pc;
-     int length;
-{
-  switch (opindex)
-    {
-    case M32R_OPERAND_SR :
-      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_DR :
-      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_SRC1 :
-      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_SRC2 :
-      print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_SCR :
-      print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_DCR :
-      print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_SIMM8 :
-      print_normal (info, fields->f_simm8, 0, pc, length);
-      break;
-    case M32R_OPERAND_SIMM16 :
-      print_normal (info, fields->f_simm16, 0, pc, length);
-      break;
-    case M32R_OPERAND_UIMM4 :
-      print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_UIMM5 :
-      print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_UIMM16 :
-      print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_ACC_S :
-      print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_ACC :
-      print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
-      break;
-    case M32R_OPERAND_HI16 :
-      print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_SLO16 :
-      print_normal (info, fields->f_simm16, 0, pc, length);
-      break;
-    case M32R_OPERAND_ULO16 :
-      print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_UIMM24 :
-      print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
-    case M32R_OPERAND_DISP8 :
-      print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
-      break;
-    case M32R_OPERAND_DISP16 :
-      print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
-      break;
-    case M32R_OPERAND_DISP24 :
-      print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
-      break;
-
-    default :
-      fprintf (stderr, "Unrecognized field %d while printing insn.\n",
-	       opindex);
-    abort ();
-  }
-}
-
-cgen_extract_fn *m32r_cgen_extract_handlers[] = {
-  0, /* default */
-  extract_insn_normal,
-};
-
-cgen_print_fn *m32r_cgen_print_handlers[] = {
-  0, /* default */
-  print_insn_normal,
-};
-
-
-void
-m32r_cgen_init_dis (mach, endian)
-     int mach;
-     enum cgen_endian endian;
-{
-  m32r_cgen_init_tables (mach);
-  cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
-  cgen_dis_init ();
-}
-
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 36ce392..59e109d 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -32,22 +32,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* Attributes.  */
 
-static const CGEN_ATTR_ENTRY MACH_attr[] = {
-  { "m32r", MACH_M32R },
-  { "m32rx", MACH_M32RX },
+static const CGEN_ATTR_ENTRY MACH_attr[] = 
+{  { "m32r", MACH_M32R },
   { 0, 0 }
 };
 
-static const CGEN_ATTR_ENTRY PIPE_attr[] = {
-  { "NONE", PIPE_NONE },
-  { "O", PIPE_O },
-  { "S", PIPE_S },
-  { "OS", PIPE_OS },
-  { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = {
-  { "ABS-ADDR", NULL },
+const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = 
+{  { "ABS-ADDR", NULL },
   { "FAKE", NULL },
   { "NEGATIVE", NULL },
   { "PC", NULL },
@@ -59,37 +50,31 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = {
   { 0, 0 }
 };
 
-const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = {
-  { "MACH", & MACH_attr[0] },
-  { "PIPE", & PIPE_attr[0] },
-  { "ALIAS", NULL },
+const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = 
+{  { "ALIAS", NULL },
   { "COND-CTI", NULL },
   { "FILL-SLOT", NULL },
-  { "PARALLEL", NULL },
   { "RELAX", NULL },
   { "RELAX-BC", NULL },
-  { "RELAX-BCL", NULL },
   { "RELAX-BL", NULL },
   { "RELAX-BNC", NULL },
-  { "RELAX-BNCL", NULL },
   { "RELAX-BRA", NULL },
   { "RELAXABLE", NULL },
   { "UNCOND-CTI", NULL },
   { 0, 0 }
 };
 
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] = {
-  { "m32r", MACH_M32R },
-  { "m32rx", MACH_M32RX }
+CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] = 
+{  { "m32r", MACH_M32R }
 };
 
-CGEN_KEYWORD m32r_cgen_opval_mach = {
-  & m32r_cgen_opval_mach_entries[0],
-  2
+CGEN_KEYWORD m32r_cgen_opval_mach = 
+{  & m32r_cgen_opval_mach_entries[0],
+  1
 };
 
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = {
-  { "fp", 13 },
+CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = 
+{  { "fp", 13 },
   { "lr", 14 },
   { "sp", 15 },
   { "r0", 0 },
@@ -110,13 +95,13 @@ CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = {
   { "r15", 15 }
 };
 
-CGEN_KEYWORD m32r_cgen_opval_h_gr = {
-  & m32r_cgen_opval_h_gr_entries[0],
+CGEN_KEYWORD m32r_cgen_opval_h_gr = 
+{  & m32r_cgen_opval_h_gr_entries[0],
   19
 };
 
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = {
-  { "psw", 0 },
+CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = 
+{  { "psw", 0 },
   { "cbr", 1 },
   { "spi", 2 },
   { "spu", 3 },
@@ -130,24 +115,14 @@ CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = {
   { "cr6", 6 }
 };
 
-CGEN_KEYWORD m32r_cgen_opval_h_cr = {
-  & m32r_cgen_opval_h_cr_entries[0],
+CGEN_KEYWORD m32r_cgen_opval_h_cr = 
+{  & m32r_cgen_opval_h_cr_entries[0],
   12
 };
 
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = {
-  { "a0", 0 },
-  { "a1", 1 }
-};
 
-CGEN_KEYWORD m32r_cgen_opval_h_accums = {
-  & m32r_cgen_opval_h_accums_entries[0],
-  2
-};
-
-
-static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = {
-  { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = 
+{  { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
   { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
   { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
   { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
@@ -159,14 +134,12 @@ static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = {
   { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
   { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
   { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[13], "h-accums", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_accums },
-  { & m32r_cgen_hw_entries[14], "h-abort", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[15], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[16], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[17], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[18], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[19], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
-  { & m32r_cgen_hw_entries[20], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
+  { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
   { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
 };
 
@@ -197,10 +170,6 @@ const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
   { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
-/* acc-s: accumulator register */
-  { "acc-s", 12, 2, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
-/* acc: accumulator reg (d) */
-  { "acc", 8, 1, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 /* hi16: high 16 bit immediate, sign optional */
   { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 /* slo16: 16 bit signed immediate, for low() */
@@ -219,101 +188,87 @@ const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
   { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 /* accum: accumulator */
   { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
-/* abort-parallel-execution: abort parallel execution */
-  { "abort-parallel-execution", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 };
 
 #define OP 1 /* syntax value for mnemonic */
 
-static const CGEN_SYNTAX syntax_table[] = {
-/* <op> $dr,$sr */
+static const CGEN_SYNTAX syntax_table[] =
+{/* <op> $dr,$sr */
 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 /* <op> $dr,$sr,$slo16 */
-/*   1 */  { OP, ' ', 130, ',', 129, ',', 143, 0 },
+/*   1 */  { OP, ' ', 130, ',', 129, ',', 141, 0 },
 /* <op> $dr,$sr,$uimm16 */
 /*   2 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 /* <op> $dr,$sr,$ulo16 */
-/*   3 */  { OP, ' ', 130, ',', 129, ',', 144, 0 },
+/*   3 */  { OP, ' ', 130, ',', 129, ',', 142, 0 },
 /* <op> $dr,$simm8 */
 /*   4 */  { OP, ' ', 130, ',', 135, 0 },
 /* <op> $dr,$sr,$simm16 */
 /*   5 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 /* <op> $disp8 */
-/*   6 */  { OP, ' ', 146, 0 },
+/*   6 */  { OP, ' ', 144, 0 },
 /* <op> $disp24 */
-/*   7 */  { OP, ' ', 148, 0 },
+/*   7 */  { OP, ' ', 146, 0 },
 /* <op> $src1,$src2,$disp16 */
-/*   8 */  { OP, ' ', 131, ',', 132, ',', 147, 0 },
+/*   8 */  { OP, ' ', 131, ',', 132, ',', 145, 0 },
 /* <op> $src2,$disp16 */
-/*   9 */  { OP, ' ', 132, ',', 147, 0 },
+/*   9 */  { OP, ' ', 132, ',', 145, 0 },
 /* <op> $src1,$src2 */
 /*  10 */  { OP, ' ', 131, ',', 132, 0 },
 /* <op> $src2,$simm16 */
 /*  11 */  { OP, ' ', 132, ',', 136, 0 },
 /* <op> $src2,$uimm16 */
 /*  12 */  { OP, ' ', 132, ',', 139, 0 },
-/* <op> $src2 */
-/*  13 */  { OP, ' ', 132, 0 },
 /* <op> $sr */
-/*  14 */  { OP, ' ', 129, 0 },
+/*  13 */  { OP, ' ', 129, 0 },
 /* <op> $dr,@$sr */
-/*  15 */  { OP, ' ', 130, ',', '@', 129, 0 },
+/*  14 */  { OP, ' ', 130, ',', '@', 129, 0 },
 /* <op> $dr,@($sr) */
-/*  16 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
+/*  15 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 /* <op> $dr,@($slo16,$sr) */
-/*  17 */  { OP, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 },
+/*  16 */  { OP, ' ', 130, ',', '@', '(', 141, ',', 129, ')', 0 },
 /* <op> $dr,@($sr,$slo16) */
-/*  18 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 },
+/*  17 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 141, ')', 0 },
 /* <op> $dr,@$sr+ */
-/*  19 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
+/*  18 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 /* <op> $dr,$uimm24 */
-/*  20 */  { OP, ' ', 130, ',', 145, 0 },
+/*  19 */  { OP, ' ', 130, ',', 143, 0 },
 /* <op> $dr,$slo16 */
-/*  21 */  { OP, ' ', 130, ',', 143, 0 },
-/* <op> $src1,$src2,$acc */
-/*  22 */  { OP, ' ', 131, ',', 132, ',', 141, 0 },
+/*  20 */  { OP, ' ', 130, ',', 141, 0 },
 /* <op> $dr */
-/*  23 */  { OP, ' ', 130, 0 },
-/* <op> $dr,$accs */
-/*  24 */  { OP, ' ', 130, ',', 141, 0 },
+/*  21 */  { OP, ' ', 130, 0 },
 /* <op> $dr,$scr */
-/*  25 */  { OP, ' ', 130, ',', 133, 0 },
+/*  22 */  { OP, ' ', 130, ',', 133, 0 },
 /* <op> $src1 */
-/*  26 */  { OP, ' ', 131, 0 },
-/* <op> $src1,$accs */
-/*  27 */  { OP, ' ', 131, ',', 141, 0 },
+/*  23 */  { OP, ' ', 131, 0 },
 /* <op> $sr,$dcr */
-/*  28 */  { OP, ' ', 129, ',', 134, 0 },
+/*  24 */  { OP, ' ', 129, ',', 134, 0 },
 /* <op> */
-/*  29 */  { OP, 0 },
-/* <op> $acc-s */
-/*  30 */  { OP, ' ', 141, 0 },
+/*  25 */  { OP, 0 },
 /* <op> $dr,$hi16 */
-/*  31 */  { OP, ' ', 130, ',', 142, 0 },
+/*  26 */  { OP, ' ', 130, ',', 140, 0 },
 /* <op> $dr,$uimm5 */
-/*  32 */  { OP, ' ', 130, ',', 138, 0 },
+/*  27 */  { OP, ' ', 130, ',', 138, 0 },
 /* <op> $src1,@$src2 */
-/*  33 */  { OP, ' ', 131, ',', '@', 132, 0 },
+/*  28 */  { OP, ' ', 131, ',', '@', 132, 0 },
 /* <op> $src1,@($src2) */
-/*  34 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
+/*  29 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
 /* <op> $src1,@($slo16,$src2) */
-/*  35 */  { OP, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 },
+/*  30 */  { OP, ' ', 131, ',', '@', '(', 141, ',', 132, ')', 0 },
 /* <op> $src1,@($src2,$slo16) */
-/*  36 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 },
+/*  31 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 141, ')', 0 },
 /* <op> $src1,@+$src2 */
-/*  37 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
+/*  32 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
 /* <op> $src1,@-$src2 */
-/*  38 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
+/*  33 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
 /* <op> $uimm4 */
-/*  39 */  { OP, ' ', 137, 0 },
-/* <op> $dr,$src2 */
-/*  40 */  { OP, ' ', 130, ',', 132, 0 },
+/*  34 */  { OP, ' ', 137, 0 },
 };
 
 #undef OP
 
-static const CGEN_FORMAT format_table[] = {
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
+static const CGEN_FORMAT format_table[] = 
+{/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
 /*   0 */  { 16, 16, 0xf0f0 },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
 /*   1 */  { 32, 32, 0xf0f00000 },
@@ -339,1042 +294,802 @@ static const CGEN_FORMAT format_table[] = {
 /*  11 */  { 32, 32, 0xfff00000 },
 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
 /*  12 */  { 32, 32, 0xfff00000 },
-/* f-op1.number.f-r1.number.f-op2.number.f-r2.src2. */
-/*  13 */  { 16, 16, 0xfff0 },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
-/*  14 */  { 32, 32, 0xf0f0ffff },
+/*  13 */  { 32, 32, 0xf0f0ffff },
 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
-/*  15 */  { 16, 16, 0xfff0 },
+/*  14 */  { 16, 16, 0xfff0 },
 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
-/*  16 */  { 32, 32, 0xf0000000 },
+/*  15 */  { 32, 32, 0xf0000000 },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
-/*  17 */  { 32, 32, 0xf0ff0000 },
-/* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2. */
-/*  18 */  { 16, 16, 0xf070 },
+/*  16 */  { 32, 32, 0xf0ff0000 },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
-/*  19 */  { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.dr.f-op2.number.f-acc-s.acc-s.f-op3.number. */
-/*  20 */  { 16, 16, 0xf0f3 },
+/*  17 */  { 16, 16, 0xf0ff },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
-/*  21 */  { 16, 16, 0xf0f0 },
+/*  18 */  { 16, 16, 0xf0f0 },
 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
-/*  22 */  { 16, 16, 0xf0ff },
-/* f-op1.number.f-r1.src1.f-op2.number.f-acc-s.acc-s.f-op3.number. */
-/*  23 */  { 16, 16, 0xf0f3 },
+/*  19 */  { 16, 16, 0xf0ff },
 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
-/*  24 */  { 16, 16, 0xf0f0 },
+/*  20 */  { 16, 16, 0xf0f0 },
 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
-/*  25 */  { 16, 16, 0xffff },
-/* f-op1.number.f-r1.number.f-op2.number.f-acc-s.acc-s.f-op3.number. */
-/*  26 */  { 16, 16, 0xfff3 },
+/*  21 */  { 16, 16, 0xffff },
 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
-/*  27 */  { 32, 32, 0xf0ff0000 },
+/*  22 */  { 32, 32, 0xf0ff0000 },
 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
-/*  28 */  { 16, 16, 0xf0e0 },
+/*  23 */  { 16, 16, 0xf0e0 },
 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
-/*  29 */  { 32, 32, 0xf0f00000 },
+/*  24 */  { 32, 32, 0xf0f00000 },
 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
-/*  30 */  { 16, 16, 0xfff0 },
-/* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number. */
-/*  31 */  { 32, 32, 0xf0f0ffff },
+/*  25 */  { 16, 16, 0xfff0 },
 };
 
 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
 #define SYN(n) (& syntax_table[n])
 #define FMT(n) (& format_table[n])
 
-const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = {
-/* null first entry, end of all hash chains */
+const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] =
+{ /* null first entry, end of all hash chains */
   { { 0 }, 0 },
 /* add $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "add", "add", SYN (0), FMT (0), 0xa0,
-    { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* add3 $dr,$sr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* and $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "and", "and", SYN (0), FMT (0), 0xc0,
-    { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "and3", "and3", SYN (2), FMT (2), 0x80c00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* or $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "or", "or", SYN (0), FMT (0), 0xe0,
-    { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* or3 $dr,$sr,$ulo16 */
   {
     { 1, 1, 1, 1 },
     "or3", "or3", SYN (3), FMT (3), 0x80e00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* xor $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "xor", "xor", SYN (0), FMT (0), 0xd0,
-    { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* addi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "addi", "addi", SYN (4), FMT (4), 0x4000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* addv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addv", "addv", SYN (0), FMT (0), 0x80,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* addx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addx", "addx", SYN (0), FMT (0), 0x90,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* bc $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8", "bc", SYN (6), FMT (6), 0x7c00,
-    { 2, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
   },
 /* bc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
   },
 /* bc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
-    { 2, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
+    { 0, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
   },
 /* bc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { 0 } }
+    { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beq", "beq", SYN (8), FMT (8), 0xb0000000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* beqz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bgez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bgtz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* blez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bltz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bnez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bl $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8", "bl", SYN (6), FMT (6), 0x7e00,
-    { 2, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
   },
 /* bl.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
-    { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { 0 } }
   },
 /* bl $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
-    { 2, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
+    { 0, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
   },
 /* bl.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
-  },
-/* bcl $disp8 */
-  {
-    { 1, 1, 1, 1 },
-    "bcl8", "bcl", SYN (6), FMT (6), 0x7800,
-    { 2, 0|A(RELAX_BCL)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bcl.s $disp8 */
-  {
-    { 1, 1, 1, 1 },
-    "bcl8.s", "bcl.s", SYN (6), FMT (6), 0x7800,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bcl $disp24 */
-  {
-    { 1, 1, 1, 1 },
-    "bcl24", "bcl", SYN (7), FMT (7), 0xf8000000,
-    { 2, 0|A(RELAX_BCL)|A(RELAX)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bcl.l $disp24 */
-  {
-    { 1, 1, 1, 1 },
-    "bcl24.l", "bcl.l", SYN (7), FMT (7), 0xf8000000,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
   },
 /* bnc $disp8 */
   {
     { 1, 1, 1, 1 },
     "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
-    { 2, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
   },
 /* bnc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
   },
 /* bnc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
-    { 2, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
+    { 0, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
   },
 /* bnc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { 0 } }
+    { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bne", "bne", SYN (8), FMT (8), 0xb0100000,
-    { 2, 0|A(COND_CTI), { 0 } }
+    { 0, 0|A(COND_CTI), { 0 } }
   },
 /* bra $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8", "bra", SYN (6), FMT (6), 0x7f00,
-    { 2, 0|A(FILL_SLOT)|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
   },
 /* bra.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
   },
 /* bra $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24", "bra", SYN (7), FMT (7), 0xff000000,
-    { 2, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
+    { 0, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
   },
 /* bra.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
-  },
-/* bncl $disp8 */
-  {
-    { 1, 1, 1, 1 },
-    "bncl8", "bncl", SYN (6), FMT (6), 0x7900,
-    { 2, 0|A(RELAX_BNCL)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bncl.s $disp8 */
-  {
-    { 1, 1, 1, 1 },
-    "bncl8.s", "bncl.s", SYN (6), FMT (6), 0x7900,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bncl $disp24 */
-  {
-    { 1, 1, 1, 1 },
-    "bncl24", "bncl", SYN (7), FMT (7), 0xf9000000,
-    { 2, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* bncl.l $disp24 */
-  {
-    { 1, 1, 1, 1 },
-    "bncl24.l", "bncl.l", SYN (7), FMT (7), 0xf9000000,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
   },
 /* cmp $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "cmp", "cmp", SYN (10), FMT (10), 0x40,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* cmpi $src2,$simm16 */
   {
     { 1, 1, 1, 1 },
     "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* cmpu $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* cmpui $src2,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
-    { 2, 0, { [CGEN_INSN_MACH] = (1 << MACH_M32R) | (1 << MACH_M32RX) } }
-  },
-/* cmpeq $src1,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "cmpeq", "cmpeq", SYN (10), FMT (10), 0x60,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* cmpz $src2 */
-  {
-    { 1, 1, 1, 1 },
-    "cmpz", "cmpz", SYN (13), FMT (13), 0x70,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* div $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "div", "div", SYN (0), FMT (14), 0x90000000,
-    { 2, 0, { 0 } }
+    "div", "div", SYN (0), FMT (13), 0x90000000,
+    { 0, 0, { 0 } }
   },
 /* divu $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "divu", "divu", SYN (0), FMT (14), 0x90100000,
-    { 2, 0, { 0 } }
+    "divu", "divu", SYN (0), FMT (13), 0x90100000,
+    { 0, 0, { 0 } }
   },
 /* rem $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "rem", "rem", SYN (0), FMT (14), 0x90200000,
-    { 2, 0, { 0 } }
+    "rem", "rem", SYN (0), FMT (13), 0x90200000,
+    { 0, 0, { 0 } }
   },
 /* remu $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "remu", "remu", SYN (0), FMT (14), 0x90300000,
-    { 2, 0, { 0 } }
-  },
-/* jc $sr */
-  {
-    { 1, 1, 1, 1 },
-    "jc", "jc", SYN (14), FMT (15), 0x1cc0,
-    { 2, 0|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* jnc $sr */
-  {
-    { 1, 1, 1, 1 },
-    "jnc", "jnc", SYN (14), FMT (15), 0x1cc0,
-    { 2, 0|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "remu", "remu", SYN (0), FMT (13), 0x90300000,
+    { 0, 0, { 0 } }
   },
 /* jl $sr */
   {
     { 1, 1, 1, 1 },
-    "jl", "jl", SYN (14), FMT (15), 0x1ec0,
-    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "jl", "jl", SYN (13), FMT (14), 0x1ec0,
+    { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* jmp $sr */
   {
     { 1, 1, 1, 1 },
-    "jmp", "jmp", SYN (14), FMT (15), 0x1fc0,
-    { 2, 0|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "jmp", "jmp", SYN (13), FMT (14), 0x1fc0,
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
 /* ld $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "ld", "ld", SYN (15), FMT (0), 0x20c0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ld", "ld", SYN (14), FMT (0), 0x20c0,
+    { 0, 0, { 0 } }
   },
 /* ld $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
-    "ld-2", "ld", SYN (16), FMT (0), 0x20c0,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ld-2", "ld", SYN (15), FMT (0), 0x20c0,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
-    "ld-d", "ld", SYN (17), FMT (1), 0xa0c00000,
-    { 2, 0, { 0 } }
+    "ld-d", "ld", SYN (16), FMT (1), 0xa0c00000,
+    { 0, 0, { 0 } }
   },
 /* ld $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "ld-d2", "ld", SYN (18), FMT (1), 0xa0c00000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "ld-d2", "ld", SYN (17), FMT (1), 0xa0c00000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldb $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "ldb", "ldb", SYN (15), FMT (0), 0x2080,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldb", "ldb", SYN (14), FMT (0), 0x2080,
+    { 0, 0, { 0 } }
   },
 /* ldb $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
-    "ldb-2", "ldb", SYN (16), FMT (0), 0x2080,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldb-2", "ldb", SYN (15), FMT (0), 0x2080,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
-    "ldb-d", "ldb", SYN (17), FMT (1), 0xa0800000,
-    { 2, 0, { 0 } }
+    "ldb-d", "ldb", SYN (16), FMT (1), 0xa0800000,
+    { 0, 0, { 0 } }
   },
 /* ldb $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "ldb-d2", "ldb", SYN (18), FMT (1), 0xa0800000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "ldb-d2", "ldb", SYN (17), FMT (1), 0xa0800000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "ldh", "ldh", SYN (15), FMT (0), 0x20a0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldh", "ldh", SYN (14), FMT (0), 0x20a0,
+    { 0, 0, { 0 } }
   },
 /* ldh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
-    "ldh-2", "ldh", SYN (16), FMT (0), 0x20a0,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldh-2", "ldh", SYN (15), FMT (0), 0x20a0,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
-    "ldh-d", "ldh", SYN (17), FMT (1), 0xa0a00000,
-    { 2, 0, { 0 } }
+    "ldh-d", "ldh", SYN (16), FMT (1), 0xa0a00000,
+    { 0, 0, { 0 } }
   },
 /* ldh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "ldh-d2", "ldh", SYN (18), FMT (1), 0xa0a00000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "ldh-d2", "ldh", SYN (17), FMT (1), 0xa0a00000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldub $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "ldub", "ldub", SYN (15), FMT (0), 0x2090,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldub", "ldub", SYN (14), FMT (0), 0x2090,
+    { 0, 0, { 0 } }
   },
 /* ldub $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
-    "ldub-2", "ldub", SYN (16), FMT (0), 0x2090,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ldub-2", "ldub", SYN (15), FMT (0), 0x2090,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
-    "ldub-d", "ldub", SYN (17), FMT (1), 0xa0900000,
-    { 2, 0, { 0 } }
+    "ldub-d", "ldub", SYN (16), FMT (1), 0xa0900000,
+    { 0, 0, { 0 } }
   },
 /* ldub $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "ldub-d2", "ldub", SYN (18), FMT (1), 0xa0900000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "ldub-d2", "ldub", SYN (17), FMT (1), 0xa0900000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* lduh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "lduh", "lduh", SYN (15), FMT (0), 0x20b0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "lduh", "lduh", SYN (14), FMT (0), 0x20b0,
+    { 0, 0, { 0 } }
   },
 /* lduh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
-    "lduh-2", "lduh", SYN (16), FMT (0), 0x20b0,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "lduh-2", "lduh", SYN (15), FMT (0), 0x20b0,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
-    "lduh-d", "lduh", SYN (17), FMT (1), 0xa0b00000,
-    { 2, 0, { 0 } }
+    "lduh-d", "lduh", SYN (16), FMT (1), 0xa0b00000,
+    { 0, 0, { 0 } }
   },
 /* lduh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "lduh-d2", "lduh", SYN (18), FMT (1), 0xa0b00000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "lduh-d2", "lduh", SYN (17), FMT (1), 0xa0b00000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ld $dr,@$sr+ */
   {
     { 1, 1, 1, 1 },
-    "ld-plus", "ld", SYN (19), FMT (0), 0x20e0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "ld-plus", "ld", SYN (18), FMT (0), 0x20e0,
+    { 0, 0, { 0 } }
   },
 /* ld24 $dr,$uimm24 */
   {
     { 1, 1, 1, 1 },
-    "ld24", "ld24", SYN (20), FMT (16), 0xe0000000,
-    { 2, 0, { 0 } }
+    "ld24", "ld24", SYN (19), FMT (15), 0xe0000000,
+    { 0, 0, { 0 } }
   },
 /* ldi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* ldi8 $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* ldi $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
-    "ldi16", "ldi", SYN (21), FMT (17), 0x90f00000,
-    { 2, 0, { 0 } }
+    "ldi16", "ldi", SYN (20), FMT (16), 0x90f00000,
+    { 0, 0, { 0 } }
   },
 /* ldi16 $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
-    "ldi16a", "ldi16", SYN (21), FMT (17), 0x90f00000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "ldi16a", "ldi16", SYN (20), FMT (16), 0x90f00000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* lock $dr,@$sr */
   {
     { 1, 1, 1, 1 },
-    "lock", "lock", SYN (15), FMT (0), 0x20d0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "lock", "lock", SYN (14), FMT (0), 0x20d0,
+    { 0, 0, { 0 } }
   },
 /* machi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "machi", "machi", SYN (10), FMT (10), 0x3040,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* machi $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "machi-a", "machi", SYN (22), FMT (18), 0x3040,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* maclo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "maclo", "maclo", SYN (10), FMT (10), 0x3050,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* maclo $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "maclo-a", "maclo", SYN (22), FMT (18), 0x3050,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* macwhi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* macwhi $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "macwhi-a", "macwhi", SYN (22), FMT (18), 0x3060,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* macwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* macwlo $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "macwlo-a", "macwlo", SYN (22), FMT (18), 0x3070,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* mul $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mul", "mul", SYN (0), FMT (0), 0x1060,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
+    { 0, 0, { 0 } }
   },
 /* mulhi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mulhi $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "mulhi-a", "mulhi", SYN (22), FMT (18), 0x3000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* mullo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mullo", "mullo", SYN (10), FMT (10), 0x3010,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mullo $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "mullo-a", "mullo", SYN (22), FMT (18), 0x3010,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* mulwhi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mulwhi $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "mulwhi-a", "mulwhi", SYN (22), FMT (18), 0x3020,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* mulwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mulwlo $src1,$src2,$acc */
-  {
-    { 1, 1, 1, 1 },
-    "mulwlo-a", "mulwlo", SYN (22), FMT (18), 0x3030,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    { 0, 0, { 0 } }
   },
 /* mv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mv", "mv", SYN (0), FMT (0), 0x1080,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* mvfachi $dr */
   {
     { 1, 1, 1, 1 },
-    "mvfachi", "mvfachi", SYN (23), FMT (19), 0x50f0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mvfachi $dr,$accs */
-  {
-    { 1, 1, 1, 1 },
-    "mvfachi-a", "mvfachi", SYN (24), FMT (20), 0x50f0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "mvfachi", "mvfachi", SYN (21), FMT (17), 0x50f0,
+    { 0, 0, { 0 } }
   },
 /* mvfaclo $dr */
   {
     { 1, 1, 1, 1 },
-    "mvfaclo", "mvfaclo", SYN (23), FMT (19), 0x50f1,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mvfaclo $dr,$acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "mvfaclo-a", "mvfaclo", SYN (24), FMT (20), 0x50f1,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "mvfaclo", "mvfaclo", SYN (21), FMT (17), 0x50f1,
+    { 0, 0, { 0 } }
   },
 /* mvfacmi $dr */
   {
     { 1, 1, 1, 1 },
-    "mvfacmi", "mvfacmi", SYN (23), FMT (19), 0x50f2,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mvfacmi $dr,$acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "mvfacmi-a", "mvfacmi", SYN (24), FMT (20), 0x50f2,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "mvfacmi", "mvfacmi", SYN (21), FMT (17), 0x50f2,
+    { 0, 0, { 0 } }
   },
 /* mvfc $dr,$scr */
   {
     { 1, 1, 1, 1 },
-    "mvfc", "mvfc", SYN (25), FMT (21), 0x1090,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "mvfc", "mvfc", SYN (22), FMT (18), 0x1090,
+    { 0, 0, { 0 } }
   },
 /* mvtachi $src1 */
   {
     { 1, 1, 1, 1 },
-    "mvtachi", "mvtachi", SYN (26), FMT (22), 0x5070,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mvtachi $src1,$acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "mvtachi-a", "mvtachi", SYN (27), FMT (23), 0x5070,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "mvtachi", "mvtachi", SYN (23), FMT (19), 0x5070,
+    { 0, 0, { 0 } }
   },
 /* mvtaclo $src1 */
   {
     { 1, 1, 1, 1 },
-    "mvtaclo", "mvtaclo", SYN (26), FMT (22), 0x5071,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* mvtaclo $src1,$acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "mvtaclo-a", "mvtaclo", SYN (27), FMT (23), 0x5071,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "mvtaclo", "mvtaclo", SYN (23), FMT (19), 0x5071,
+    { 0, 0, { 0 } }
   },
 /* mvtc $sr,$dcr */
   {
     { 1, 1, 1, 1 },
-    "mvtc", "mvtc", SYN (28), FMT (24), 0x10a0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "mvtc", "mvtc", SYN (24), FMT (20), 0x10a0,
+    { 0, 0, { 0 } }
   },
 /* neg $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "neg", "neg", SYN (0), FMT (0), 0x30,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* nop */
   {
     { 1, 1, 1, 1 },
-    "nop", "nop", SYN (29), FMT (25), 0x7000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    "nop", "nop", SYN (25), FMT (21), 0x7000,
+    { 0, 0, { 0 } }
   },
 /* not $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "not", "not", SYN (0), FMT (0), 0xb0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* rac */
   {
     { 1, 1, 1, 1 },
-    "rac", "rac", SYN (29), FMT (25), 0x5090,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* rac $acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "rac-a", "rac", SYN (30), FMT (26), 0x5090,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "rac", "rac", SYN (25), FMT (21), 0x5090,
+    { 0, 0, { 0 } }
   },
 /* rach */
   {
     { 1, 1, 1, 1 },
-    "rach", "rach", SYN (29), FMT (25), 0x5080,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
-  },
-/* rach $acc-s */
-  {
-    { 1, 1, 1, 1 },
-    "rach-a", "rach", SYN (30), FMT (26), 0x5080,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "rach", "rach", SYN (25), FMT (21), 0x5080,
+    { 0, 0, { 0 } }
   },
 /* rte */
   {
     { 1, 1, 1, 1 },
-    "rte", "rte", SYN (29), FMT (25), 0x10d6,
-    { 2, 0|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "rte", "rte", SYN (25), FMT (21), 0x10d6,
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
 /* seth $dr,$hi16 */
   {
     { 1, 1, 1, 1 },
-    "seth", "seth", SYN (31), FMT (27), 0xd0c00000,
-    { 2, 0, { 0 } }
+    "seth", "seth", SYN (26), FMT (22), 0xd0c00000,
+    { 0, 0, { 0 } }
   },
 /* sll $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sll", "sll", SYN (0), FMT (0), 0x1040,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0, { 0 } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* slli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
-    "slli", "slli", SYN (32), FMT (28), 0x5040,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "slli", "slli", SYN (27), FMT (23), 0x5040,
+    { 0, 0, { 0 } }
   },
 /* sra $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sra", "sra", SYN (0), FMT (0), 0x1020,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0, { 0 } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* srai $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
-    "srai", "srai", SYN (32), FMT (28), 0x5020,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "srai", "srai", SYN (27), FMT (23), 0x5020,
+    { 0, 0, { 0 } }
   },
 /* srl $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "srl", "srl", SYN (0), FMT (0), 0x1000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    { 0, 0, { 0 } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
-    { 2, 0, { 0 } }
+    { 0, 0, { 0 } }
   },
 /* srli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
-    "srli", "srli", SYN (32), FMT (28), 0x5000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "srli", "srli", SYN (27), FMT (23), 0x5000,
+    { 0, 0, { 0 } }
   },
 /* st $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
-    "st", "st", SYN (33), FMT (10), 0x2040,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "st", "st", SYN (28), FMT (10), 0x2040,
+    { 0, 0, { 0 } }
   },
 /* st $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
-    "st-2", "st", SYN (34), FMT (10), 0x2040,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "st-2", "st", SYN (29), FMT (10), 0x2040,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
-    "st-d", "st", SYN (35), FMT (29), 0xa0400000,
-    { 2, 0, { 0 } }
+    "st-d", "st", SYN (30), FMT (24), 0xa0400000,
+    { 0, 0, { 0 } }
   },
 /* st $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "st-d2", "st", SYN (36), FMT (29), 0xa0400000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "st-d2", "st", SYN (31), FMT (24), 0xa0400000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* stb $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
-    "stb", "stb", SYN (33), FMT (10), 0x2000,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "stb", "stb", SYN (28), FMT (10), 0x2000,
+    { 0, 0, { 0 } }
   },
 /* stb $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
-    "stb-2", "stb", SYN (34), FMT (10), 0x2000,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "stb-2", "stb", SYN (29), FMT (10), 0x2000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
-    "stb-d", "stb", SYN (35), FMT (29), 0xa0000000,
-    { 2, 0, { 0 } }
+    "stb-d", "stb", SYN (30), FMT (24), 0xa0000000,
+    { 0, 0, { 0 } }
   },
 /* stb $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "stb-d2", "stb", SYN (36), FMT (29), 0xa0000000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "stb-d2", "stb", SYN (31), FMT (24), 0xa0000000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* sth $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
-    "sth", "sth", SYN (33), FMT (10), 0x2020,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "sth", "sth", SYN (28), FMT (10), 0x2020,
+    { 0, 0, { 0 } }
   },
 /* sth $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
-    "sth-2", "sth", SYN (34), FMT (10), 0x2020,
-    { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "sth-2", "sth", SYN (29), FMT (10), 0x2020,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
-    "sth-d", "sth", SYN (35), FMT (29), 0xa0200000,
-    { 2, 0, { 0 } }
+    "sth-d", "sth", SYN (30), FMT (24), 0xa0200000,
+    { 0, 0, { 0 } }
   },
 /* sth $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
-    "sth-d2", "sth", SYN (36), FMT (29), 0xa0200000,
-    { 2, 0|A(ALIAS), { 0 } }
+    "sth-d2", "sth", SYN (31), FMT (24), 0xa0200000,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* st $src1,@+$src2 */
   {
     { 1, 1, 1, 1 },
-    "st-plus", "st", SYN (37), FMT (10), 0x2060,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "st-plus", "st", SYN (32), FMT (10), 0x2060,
+    { 0, 0, { 0 } }
   },
 /* st $src1,@-$src2 */
   {
     { 1, 1, 1, 1 },
-    "st-minus", "st", SYN (38), FMT (10), 0x2070,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "st-minus", "st", SYN (33), FMT (10), 0x2070,
+    { 0, 0, { 0 } }
   },
 /* sub $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sub", "sub", SYN (0), FMT (0), 0x20,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* subv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subv", "subv", SYN (0), FMT (0), 0x0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* subx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subx", "subx", SYN (0), FMT (0), 0x10,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
+    { 0, 0, { 0 } }
   },
 /* trap $uimm4 */
   {
     { 1, 1, 1, 1 },
-    "trap", "trap", SYN (39), FMT (30), 0x10f0,
-    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
+    "trap", "trap", SYN (34), FMT (25), 0x10f0,
+    { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* unlock $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
-    "unlock", "unlock", SYN (33), FMT (10), 0x2050,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
+    "unlock", "unlock", SYN (28), FMT (10), 0x2050,
+    { 0, 0, { 0 } }
   },
 /* push $src1 */
   {
     { 1, 1, 1, 1 },
-    "push", "push", SYN (26), FMT (22), 0x207f,
-    { 2, 0|A(ALIAS), { 0 } }
+    "push", "push", SYN (23), FMT (19), 0x207f,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 /* pop $dr */
   {
     { 1, 1, 1, 1 },
-    "pop", "pop", SYN (23), FMT (19), 0x20ef,
-    { 2, 0|A(ALIAS), { 0 } }
-  },
-/* satb $dr,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "satb", "satb", SYN (40), FMT (31), 0x80000100,
-    { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* sath $dr,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "sath", "sath", SYN (40), FMT (31), 0x80000200,
-    { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* sat $dr,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "sat", "sat", SYN (40), FMT (31), 0x80000000,
-    { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* pcmpbz $src2 */
-  {
-    { 1, 1, 1, 1 },
-    "pcmpbz", "pcmpbz", SYN (13), FMT (13), 0x370,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* sadd */
-  {
-    { 1, 1, 1, 1 },
-    "sadd", "sadd", SYN (29), FMT (25), 0x50e4,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* macwu1 $src1,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "macwu1", "macwu1", SYN (10), FMT (10), 0x50b0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* msblo $src1,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "msblo", "msblo", SYN (10), FMT (10), 0x50d0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* mulwu1 $src1,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "mulwu1", "mulwu1", SYN (10), FMT (10), 0x50a0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* machl1 $src1,$src2 */
-  {
-    { 1, 1, 1, 1 },
-    "machl1", "machl1", SYN (10), FMT (10), 0x50c0,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* sc */
-  {
-    { 1, 1, 1, 1 },
-    "sc", "sc", SYN (29), FMT (25), 0x7401,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
-  },
-/* snc */
-  {
-    { 1, 1, 1, 1 },
-    "snc", "snc", SYN (29), FMT (25), 0x7501,
-    { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
+    "pop", "pop", SYN (21), FMT (17), 0x20ef,
+    { 0, 0|A(ALIAS), { 0 } }
   },
 };
 
@@ -1382,7 +1097,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = {
 #undef SYN
 #undef FMT
 
-CGEN_INSN_TABLE m32r_cgen_insn_table = {
+CGEN_INSN_TABLE m32r_cgen_insn_table =
+{
   & m32r_cgen_insn_table_entries[0],
   sizeof (CGEN_INSN),
   CGEN_NUM_INSNS,
@@ -1396,21 +1112,21 @@ CGEN_INSN_TABLE m32r_cgen_insn_table = {
 
 unsigned int
 m32r_cgen_asm_hash_insn (insn)
-     const char *insn;
+     const char * insn;
 {
   return CGEN_ASM_HASH (insn);
 }
 
 unsigned int
 m32r_cgen_dis_hash_insn (buf, value)
-     const char *buf;
+     const char *  buf;
      unsigned long value;
 {
   return CGEN_DIS_HASH (buf, value);
 }
 
-CGEN_OPCODE_DATA m32r_cgen_opcode_data = {
-  & m32r_cgen_hw_entries[0],
+CGEN_OPCODE_DATA m32r_cgen_opcode_data = 
+{  & m32r_cgen_hw_entries[0],
   & m32r_cgen_insn_table,
 };
 
@@ -1425,70 +1141,64 @@ m32r_cgen_init_tables (mach)
 CGEN_INLINE void
 m32r_cgen_set_operand (opindex, valuep, fields)
      int opindex;
-     const long *valuep;
-     CGEN_FIELDS *fields;
+     const long *  valuep;
+     CGEN_FIELDS * fields;
 {
   switch (opindex)
     {
     case M32R_OPERAND_SR :
-      fields->f_r2 = *valuep;
+      fields->f_r2 = * valuep;
       break;
     case M32R_OPERAND_DR :
-      fields->f_r1 = *valuep;
+      fields->f_r1 = * valuep;
       break;
     case M32R_OPERAND_SRC1 :
-      fields->f_r1 = *valuep;
+      fields->f_r1 = * valuep;
       break;
     case M32R_OPERAND_SRC2 :
-      fields->f_r2 = *valuep;
+      fields->f_r2 = * valuep;
       break;
     case M32R_OPERAND_SCR :
-      fields->f_r2 = *valuep;
+      fields->f_r2 = * valuep;
       break;
     case M32R_OPERAND_DCR :
-      fields->f_r1 = *valuep;
+      fields->f_r1 = * valuep;
       break;
     case M32R_OPERAND_SIMM8 :
-      fields->f_simm8 = *valuep;
+      fields->f_simm8 = * valuep;
       break;
     case M32R_OPERAND_SIMM16 :
-      fields->f_simm16 = *valuep;
+      fields->f_simm16 = * valuep;
       break;
     case M32R_OPERAND_UIMM4 :
-      fields->f_uimm4 = *valuep;
+      fields->f_uimm4 = * valuep;
       break;
     case M32R_OPERAND_UIMM5 :
-      fields->f_uimm5 = *valuep;
+      fields->f_uimm5 = * valuep;
       break;
     case M32R_OPERAND_UIMM16 :
-      fields->f_uimm16 = *valuep;
-      break;
-    case M32R_OPERAND_ACC_S :
-      fields->f_acc_s = *valuep;
-      break;
-    case M32R_OPERAND_ACC :
-      fields->f_acc = *valuep;
+      fields->f_uimm16 = * valuep;
       break;
     case M32R_OPERAND_HI16 :
-      fields->f_hi16 = *valuep;
+      fields->f_hi16 = * valuep;
       break;
     case M32R_OPERAND_SLO16 :
-      fields->f_simm16 = *valuep;
+      fields->f_simm16 = * valuep;
       break;
     case M32R_OPERAND_ULO16 :
-      fields->f_uimm16 = *valuep;
+      fields->f_uimm16 = * valuep;
       break;
     case M32R_OPERAND_UIMM24 :
-      fields->f_uimm24 = *valuep;
+      fields->f_uimm24 = * valuep;
       break;
     case M32R_OPERAND_DISP8 :
-      fields->f_disp8 = *valuep;
+      fields->f_disp8 = * valuep;
       break;
     case M32R_OPERAND_DISP16 :
-      fields->f_disp16 = *valuep;
+      fields->f_disp16 = * valuep;
       break;
     case M32R_OPERAND_DISP24 :
-      fields->f_disp24 = *valuep;
+      fields->f_disp24 = * valuep;
       break;
 
     default :
@@ -1502,8 +1212,8 @@ m32r_cgen_set_operand (opindex, valuep, fields)
 
 CGEN_INLINE long
 m32r_cgen_get_operand (opindex, fields)
-     int opindex;
-     const CGEN_FIELDS *fields;
+     int                 opindex;
+     const CGEN_FIELDS * fields;
 {
   long value;
 
@@ -1542,12 +1252,6 @@ m32r_cgen_get_operand (opindex, fields)
     case M32R_OPERAND_UIMM16 :
       value = fields->f_uimm16;
       break;
-    case M32R_OPERAND_ACC_S :
-      value = fields->f_acc_s;
-      break;
-    case M32R_OPERAND_ACC :
-      value = fields->f_acc;
-      break;
     case M32R_OPERAND_HI16 :
       value = fields->f_hi16;
       break;
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 0c8f2f0..4c3b52e 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -39,11 +39,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_INT_INSN
 
 /* +1 because the first entry is reserved (null) */
-#define CGEN_NUM_INSNS (165 + 1)
-#define CGEN_NUM_OPERANDS (24)
+#define CGEN_NUM_INSNS (127 + 1)
+#define CGEN_NUM_OPERANDS (21)
 
 /* Number of non-boolean attributes. */
-#define CGEN_MAX_INSN_ATTRS 2
+#define CGEN_MAX_INSN_ATTRS 0
 #define CGEN_MAX_OPERAND_ATTRS 0
 
 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
@@ -54,7 +54,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define CGEN_MNEMONIC_OPERANDS
 
 /* Number of architecture variants.  */
-#define MAX_MACHS 2
+#define MAX_MACHS 1
 
 /* Enums.  */
 
@@ -79,23 +79,18 @@ typedef enum cgen_operand_type {
   M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
   M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
   M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
-  M32R_OPERAND_ACC_S = 12, M32R_OPERAND_ACC = 13, M32R_OPERAND_HI16 = 14, M32R_OPERAND_SLO16 = 15,
-  M32R_OPERAND_ULO16 = 16, M32R_OPERAND_UIMM24 = 17, M32R_OPERAND_DISP8 = 18, M32R_OPERAND_DISP16 = 19,
-  M32R_OPERAND_DISP24 = 20, M32R_OPERAND_CONDBIT = 21, M32R_OPERAND_ACCUM = 22, M32R_OPERAND_ABORT_PARALLEL_EXECUTION = 23
+  M32R_OPERAND_HI16 = 12, M32R_OPERAND_SLO16 = 13, M32R_OPERAND_ULO16 = 14, M32R_OPERAND_UIMM24 = 15,
+  M32R_OPERAND_DISP8 = 16, M32R_OPERAND_DISP16 = 17, M32R_OPERAND_DISP24 = 18, M32R_OPERAND_CONDBIT = 19,
+  M32R_OPERAND_ACCUM = 20
 } CGEN_OPERAND_TYPE;
 
 /* Non-boolean attributes.  */
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_M32R = 0, MACH_M32RX = 1
+  MACH_M32R = 0
 } MACH_ATTR;
 
-/* Enum declaration for parallel execution pipeline selection.  */
-typedef enum pipe_attr {
-  PIPE_NONE = 0, PIPE_O = 1, PIPE_S = 2, PIPE_OS = 3
-} PIPE_ATTR;
-
 /* Operand and instruction attribute indices.  */
 
 /* Enum declaration for cgen_operand attrs.  */
@@ -107,10 +102,9 @@ typedef enum cgen_operand_attr {
 
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
-  CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI,
-  CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAX_BC,
-  CGEN_INSN_RELAX_BCL, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BNCL,
-  CGEN_INSN_RELAX_BRA, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
+  CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_RELAX,
+  CGEN_INSN_RELAX_BC, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BRA,
+  CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 } CGEN_INSN_ATTR;
 
 /* Insn types are used by the simulator.  */
@@ -123,41 +117,32 @@ typedef enum cgen_insn_type {
   M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
   M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
   M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
-  M32R_INSN_BCL8, M32R_INSN_BCL8_S, M32R_INSN_BCL24, M32R_INSN_BCL24_L,
   M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
   M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
-  M32R_INSN_BRA24_L, M32R_INSN_BNCL8, M32R_INSN_BNCL8_S, M32R_INSN_BNCL24,
-  M32R_INSN_BNCL24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
-  M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV,
-  M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_JC,
-  M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
+  M32R_INSN_BRA24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
+  M32R_INSN_CMPUI, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM,
+  M32R_INSN_REMU, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
   M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
   M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
   M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
   M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
   M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
   M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
-  M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A,
-  M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A,
-  M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI,
-  M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI,
-  M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV,
-  M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A,
-  M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI,
-  M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC,
-  M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC,
-  M32R_INSN_RAC_A, M32R_INSN_RACH, M32R_INSN_RACH_A, M32R_INSN_RTE,
-  M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI,
-  M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL,
-  M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_2,
-  M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2,
-  M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2,
-  M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS,
-  M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP,
-  M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP, M32R_INSN_SATB,
-  M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ, M32R_INSN_SADD,
-  M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1, M32R_INSN_MACHL1,
-  M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX
+  M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACLO,
+  M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI,
+  M32R_INSN_MULLO, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV,
+  M32R_INSN_MVFACHI, M32R_INSN_MVFACLO, M32R_INSN_MVFACMI, M32R_INSN_MVFC,
+  M32R_INSN_MVTACHI, M32R_INSN_MVTACLO, M32R_INSN_MVTC, M32R_INSN_NEG,
+  M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, M32R_INSN_RACH,
+  M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3,
+  M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI,
+  M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST,
+  M32R_INSN_ST_2, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB,
+  M32R_INSN_STB_2, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH,
+  M32R_INSN_STH_2, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS,
+  M32R_INSN_ST_MINUS, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX,
+  M32R_INSN_TRAP, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP,
+  M32R_INSN_MAX
 } CGEN_INSN_TYPE;
 
 /* Index of `illegal' insn place holder.  */
@@ -169,8 +154,8 @@ typedef enum cgen_insn_type {
 #include "opcode/cgen.h"
 
 /* This struct records data prior to insertion or after extraction.  */
-typedef struct cgen_fields {
-  long f_nil;
+typedef struct cgen_fields 
+{  long f_nil;
   long f_op1;
   long f_op2;
   long f_cond;
@@ -187,10 +172,6 @@ typedef struct cgen_fields {
   long f_disp8;
   long f_disp16;
   long f_disp24;
-  long f_op23;
-  long f_op3;
-  long f_acc;
-  long f_acc_s;
   int length;
 } CGEN_FIELDS;
 
@@ -201,7 +182,6 @@ extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 extern CGEN_KEYWORD m32r_cgen_opval_mach;
 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
-extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 
 #define CGEN_INIT_PARSE() \
 {\