Add MIPS32 as a seperate MIPS architecture

4 files changed, 84 insertions, 66 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6bac17d..a03baa3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -17,6 +17,14 @@
         MIPS32 "sdbbp" to use 'B' operand specifier.  Add MIPS32
         "wait" variant which uses 'J' operand specifier.
         
+        * mips-dis.c (set_mips_isa_type): Update to use
+        CPU_UNKNOWN and ISA_* constants.  Add bfd_mach_mips32 case.
+        Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
+        * mips-opc.c (I32): New constant for instructions added in
+        MIPS32.
+        (P4): Delete.
+        (mips_builtin_opcodes) Replace all uses of P4 with I32.
+
 2000-11-28  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 39bcf33..bb970ef 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -287,8 +287,8 @@ set_mips_isa_type (mach, isa, cputype)
      int *isa;
      int *cputype;
 {
-  int target_processor = 0;
-  int mips_isa = 0;
+  int target_processor = CPU_UNKNOWN;
+  int mips_isa = ISA_UNKNOWN;
 
   /* Use standard MIPS register names by default.  */
   reg_names = std_reg_names;
@@ -297,71 +297,75 @@ set_mips_isa_type (mach, isa, cputype)
     {
     case bfd_mach_mips3000:
       target_processor = CPU_R3000;
-      mips_isa = 1;
+      mips_isa = ISA_MIPS1;
       break;
     case bfd_mach_mips3900:
       target_processor = CPU_R3900;
-      mips_isa = 1;
+      mips_isa = ISA_MIPS1;
       break;
     case bfd_mach_mips4000:
       target_processor = CPU_R4000;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4010:
       target_processor = CPU_R4010;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS2;
       break;
     case bfd_mach_mips4100:
       target_processor = CPU_VR4100;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4111:
       target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4300:
       target_processor = CPU_R4300;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4400:
       target_processor = CPU_R4400;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4600:
       target_processor = CPU_R4600;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips4650:
       target_processor = CPU_R4650;
-      mips_isa = 3;
-      break;
-    case bfd_mach_mips4K:
-      target_processor = CPU_4K;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS3;
       break;
     case bfd_mach_mips5000:
       target_processor = CPU_R5000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips6000:
       target_processor = CPU_R6000;
-      mips_isa = 2;
+      mips_isa = ISA_MIPS2;
       break;
     case bfd_mach_mips8000:
       target_processor = CPU_R8000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips10000:
       target_processor = CPU_R10000;
-      mips_isa = 4;
+      mips_isa = ISA_MIPS4;
       break;
     case bfd_mach_mips16:
       target_processor = CPU_MIPS16;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
+      break;
+    case bfd_mach_mips32:
+      target_processor = CPU_MIPS32;
+      mips_isa = ISA_MIPS32;
+      break;
+    case bfd_mach_mips32_4k:
+      target_processor = CPU_MIPS32_4K;
+      mips_isa = ISA_MIPS32;
       break;
     default:
       target_processor = CPU_R3000;
-      mips_isa = 3;
+      mips_isa = ISA_MIPS3;
       break;
     }
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 3e19ffa..622a231 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -77,8 +77,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I3	INSN_ISA3
 #define I4	INSN_ISA4
 #define I5	INSN_ISA5
+#define I32	INSN_ISA32
+
 #define P3	INSN_4650
-#define P4	INSN_MIPS32
 #define L1	INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
@@ -113,9 +114,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,	match,	    mask,	pinfo,          membership */
-{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           G3|M1|P4},
+{"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           G3|M1|I32},
 {"nop",     "",         0x00000000, 0xffffffff, 0,              I1      },
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,              M1|P4   },
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,              M1|I32  },
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,		I1	}, /* addiu */
 {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,		I1	}, /* ori */
 {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,	I1	},
@@ -223,7 +224,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 	I2|T3	},
 {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,	I2	},
 {"break",   "",		0x0000000d, 0xffffffff,	TRAP,		I1	},
-{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           P4      },
+{"break",   "B",        0x0000000d, 0xfc00003f, TRAP,           I32     },
 {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,		I1	},
 {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,		I1	},
 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I1	},
@@ -322,7 +323,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.ngt.s", "M,S,T",	0x4600003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	I4|M1	},
 {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
 {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	I5	},
-{"cache",   "k,o(b)",	0xbc000000, 0xfc000000, RD_b,		I3|T3|M1|P4	},
+{"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           I3|T3|M1|I32    },
 {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
 {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
 {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
@@ -332,8 +333,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	I1	},
 {"cfc2",    "t,G",	0x48400000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
 {"cfc3",    "t,G",	0x4c400000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
-{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|RD_s,      P4      },
-{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|RD_s,      P4      },
+{"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|RD_s,      I32     },
+{"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|RD_s,      I32     },
 {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,	I1	},
 {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
 {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	I1	},
@@ -362,7 +363,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,	I3	},
 {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,	I3	},
-{"deret",   "",         0x4200001f, 0xffffffff,    0,	G2|M1|P4	},
+{"deret",   "",         0x4200001f, 0xffffffff, 0,      G2|M1|I32       },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",	0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,	I3	},
 {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,	I3	},
@@ -434,7 +435,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,	I3	},
 {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,	I3	},
 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,	I3	},
-{"eret",    "",		0x42000018, 0xffffffff,	0,	I3|M1|P4	},
+{"eret",    "",         0x42000018, 0xffffffff, 0,              I3|M1|I32},
 {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,	I3	},
 {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,	I3	},
 {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,	I2	},
@@ -531,29 +532,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,	I3	},
 {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,	I3	},
 {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,	I4	},
-{"mad",	    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
-{"madu",    "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P3|P4	},
+{"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|I32  },
+{"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3|I32  },
 {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I4	},
 {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
 {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
 {"madd",    "s,t",	0x0000001c, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
-{"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
+{"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"madd",    "s,t",	0x70000000, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	        G1|M1	},
 {"madd",    "d,s,t",	0x70000000, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1	},
 {"maddu",   "s,t",	0x0000001d, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,		L1	},
-{"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
+{"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"maddu",   "s,t",	0x70000001, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|IS_M,	G1|M1},
 {"maddu",   "d,s,t",	0x70000001, 0xfc0007ff,	RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,	G1},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	V1	},
 {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,	I1	},
-{"mfc0",    "t,G,H",	0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,	P4	},
+{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32     },
 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
 {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1},
-{"mfc1",    "t,G,H",    0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,     P4},
+{"mfc1",    "t,G,H",    0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S,     I32},
 {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,	I1	},
-{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4      },
+{"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32     },
 {"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,	I1	},
-{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4      },
+{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32     },
 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,	I1	},
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,	I1	},
 {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,	I1	},
@@ -563,7 +564,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.d",  "D,S,N",	0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
 {"movf.s",  "D,S,N",	0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5	},
-{"movn",    "d,v,t",	0x0000000b, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32       },
 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,L1	},
 {"movn.d",  "D,S,t",	0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
 {"movn.s",  "D,S,t",	0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
@@ -571,7 +572,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.d",  "D,S,N",	0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I4|M1	},
 {"movt.s",  "D,S,N",	0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,	I4|M1	},
 {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	I5},
-{"movz",    "d,v,t",	0x0000000a, 0xfc0007ff,	WR_d|RD_s|RD_t,	I4|M1|P4	},
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32       },
 {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,L1	},
 {"movz.d",  "D,S,t",	0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,	I4|M1	},
 {"movz.s",  "D,S,t",	0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,	I4|M1	},
@@ -580,24 +581,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,	I4	},
 {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,	I5	},
 {"msub",    "s,t",	0x0000001e, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
-{"msub",    "s,t",	0x70000004, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
+{"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"msubu",   "s,t",	0x0000001f, 0xfc00ffff,	RD_s|RD_t|WR_HI|WR_LO,L1	},
-{"msubu",   "s,t",	0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,	P4	},
+{"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      I32     },
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
-{"mtc0",    "t,G,H",	0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,	P4	},
+{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
 {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
-{"mtc1",    "t,G,H",    0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,     P4      },
+{"mtc1",    "t,G,H",    0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S,     I32     },
 {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
-{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   P4      },
+{"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
 {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	I1	},
-{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   P4      },
+{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,	I1	},
 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,	I1	},
 {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I1	},
 {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	I1	},
 {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	I5	},
-{"mul",     "d,v,t",	0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,	P3|P4	},
+{"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,     P3|I32  },
 {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,	I1	},
 {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,	I1	},
 {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,	I1	},
@@ -667,7 +668,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           G2|M1	},
 {"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,		G2|M1	},
 {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,		G2|M1	},
-{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           P4      },
+{"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           I32     },
 {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
 {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	I2	},
 {"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,	I2	},
@@ -775,10 +776,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
 {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,	I2		}, /* tgeiu */
 {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,	I2	},
-{"tlbp",    "",		0x42000008, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
-{"tlbr",    "",		0x42000001, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
-{"tlbwi",   "",		0x42000002, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
-{"tlbwr",   "",		0x42000006, 0xffffffff,	INSN_TLB,	I1|M1|P4	},
+{"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       I1|M1|I32       },
+{"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       I1|M1|I32       },
 {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,	I2		},
 {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,	I2	 },
 {"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,	I2	 },
@@ -819,8 +820,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,	I1	},
 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,	I1	},
 {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,	I1	},
-{"wait",    "",		0x42000020, 0xffffffff,	TRAP,	I3|M1|P4	},
-{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   P4      },
+{"wait",    "",         0x42000020, 0xffffffff, TRAP,   I3|M1|I32       },
+{"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   I32     },
 {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,	L1	},
 {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,	L1	},
 /* No hazard protection on coprocessor instructions--they shouldn't
diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot
index ab99ee1..f65a42b 100644
--- a/opcodes/po/opcodes.pot
+++ b/opcodes/po/opcodes.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-09-05 17:03-0700\n"
+"POT-Creation-Date: 2000-12-01 13:18-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -22,7 +22,8 @@ msgstr ""
 msgid "jump hint unaligned"
 msgstr ""
 
-#: arc-dis.c:232
+#. Default text to print if an instruction isn't recognized.
+#: arc-dis.c:232 fr30-dis.c:39 m32r-dis.c:39
 msgid "*unknown*"
 msgstr ""
 
@@ -48,21 +49,21 @@ msgstr ""
 msgid "branch address not on 4 byte boundary"
 msgstr ""
 
-#: arm-dis.c:466
+#: arm-dis.c:489
 msgid "<illegal precision>"
 msgstr ""
 
-#: arm-dis.c:878
+#: arm-dis.c:904
 #, c-format
 msgid "Unrecognised register name set: %s\n"
 msgstr ""
 
-#: arm-dis.c:885
+#: arm-dis.c:911
 #, c-format
 msgid "Unrecognised disassembler option: %s\n"
 msgstr ""
 
-#: arm-dis.c:1049
+#: arm-dis.c:1075
 msgid ""
 "\n"
 "The following ARM specific disassembler options are supported for use with\n"
@@ -203,6 +204,10 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
+#: i386-dis.c:1949
+msgid "<internal disassembler error>"
+msgstr ""
+
 #: m10200-dis.c:199
 #, c-format
 msgid "unknown\t0x%02x"
@@ -233,7 +238,7 @@ msgstr ""
 msgid "# <dis error: %08x>"
 msgstr ""
 
-#: mips-dis.c:242
+#: mips-dis.c:273
 #, c-format
 msgid "# internal error, undefined modifier(%c)"
 msgstr ""
@@ -277,21 +282,21 @@ msgid "invalid register operand when updating"
 msgstr ""
 
 #. Mark as non-valid instruction
-#: sparc-dis.c:743
+#: sparc-dis.c:748
 msgid "unknown"
 msgstr ""
 
-#: sparc-dis.c:815
+#: sparc-dis.c:823
 #, c-format
 msgid "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:826
+#: sparc-dis.c:834
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
 msgstr ""
 
-#: sparc-dis.c:875
+#: sparc-dis.c:883
 #, c-format
 msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
 msgstr ""