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authorMaciej W. Rozycki <macro@imgtec.com>2016-12-23 19:40:51 +0000
committerMaciej W. Rozycki <macro@imgtec.com>2016-12-23 19:55:21 +0000
commit5284e471d53ccb7c7a1d140bd83098607ccf4b8a (patch)
treeb0c7d481500be41b59a1f8ab540dd25e9e20c599 /opcodes
parentbdd152861ce75c36828904cf3d10f8ce14da6cf5 (diff)
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MIPS16: Add ASMACRO instruction support
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/mips16-opc.c9
2 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 469113f..4f336ce 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
+ `4' and `s' operand codes.
+ (mips16_opcodes): Add "asmacro" entry.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
* mips-dis.c (print_mips16_insn_arg): Simplify processing of
extended operands.
* mips16-opc.c (decode_mips16_operand): Switch the extended
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index d102b8c..134630b 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -51,6 +51,11 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
{
case '.': MAPPED_REG (0, 0, GP, reg_0_map);
+ case '0': HINT (5, 0);
+ case '1': HINT (3, 5);
+ case '2': HINT (3, 8);
+ case '3': HINT (5, 16);
+ case '4': HINT (3, 21);
case '6': UINT (6, 5);
case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
@@ -67,6 +72,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case 'i': JALX (26, 0, 2);
case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
+ case 's': HINT (3, 24);
case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
@@ -357,6 +363,9 @@ const struct mips_opcode mips16_opcodes[] =
{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
+ /* Place asmacro at the bottom so that it catches any implementation
+ specific macros that didn't match anything. */
+{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
/* Place EXTEND last so that it catches any prefix that didn't match
anything. */
{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },