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| author | Alan Modra <amodra@gmail.com> | 2021-03-29 09:44:48 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2021-03-29 11:22:21 +1030 |
| commit | 3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e (patch) | |
| tree | a8319153e59bc6cc27da4ff12bfa95ee923019ff /opcodes | |
| parent | f4f9ede04272c1417b187afe6964e5c0687f1904 (diff) | |
| download | gdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.zip gdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.tar.gz gdb-3d7d6c1b507b4a5c4b991dd4158c35d91539aa8e.tar.bz2 | |
opcodes int vs bfd_boolean fixes
cpu/
* frv.opc (frv_is_branch_major, frv_is_float_major),
(frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
(frv_is_media_insn, spr_valid): Correct prototypes.
include/
* opcode/aarch64.h (aarch64_opcode_encode): Correct prototype.
opcodes/
* arc-dis.c (extract_operand_value): Correct NULL cast.
* frv-opc.h: Regenerate.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arc-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/frv-opc.h | 18 |
3 files changed, 15 insertions, 10 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0e2e94c..7a531b3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-03-29 Alan Modra <amodra@gmail.com> + + * arc-dis.c (extract_operand_value): Correct NULL cast. + * frv-opc.h: Regenerate. + 2021-03-26 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 0c9b379..a7e2db1 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -694,7 +694,7 @@ extract_operand_value (const struct arc_operand *operand, else { if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); + value = (*operand->extract) (insn, (bfd_boolean *) NULL); else { if (operand->flags & ARC_OPERAND_ALIGNED32) diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 9fc6922..95f4797 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -58,15 +58,15 @@ typedef struct const CGEN_INSN * insn[FRV_VLIW_SIZE]; } FRV_VLIW; -int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_branch_insn (const CGEN_INSN *); -int frv_is_float_insn (const CGEN_INSN *); -int frv_is_media_insn (const CGEN_INSN *); -void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); -int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); -int spr_valid (long); +bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +bfd_boolean frv_is_branch_insn (const CGEN_INSN *); +bfd_boolean frv_is_float_insn (const CGEN_INSN *); +bfd_boolean frv_is_media_insn (const CGEN_INSN *); +void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); +int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); +bfd_boolean spr_valid (long); /* -- */ /* Enum declaration for frv instruction types. */ typedef enum cgen_insn_type { |