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authorJose E. Marchesi <jose.marchesi@oracle.com>2017-05-19 09:27:08 -0700
committerJose E. Marchesi <jose.marchesi@oracle.com>2017-05-19 09:27:08 -0700
commit64517994807b0d6bb3c6fd106f117c03242fac72 (patch)
tree1bf70aa6ad0c1e8278ffe7bafa54e6b88b8d0fd0 /opcodes/sparc-dis.c
parent92f7d783c1038841beacaba28a5f5d740a5ccad6 (diff)
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binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA 2017) to binutils. New instructions: - Dictionary Unpack + dictunpack - Partitioned Compare with shifted result + Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl - Partitioned Dual-Equal compared, with shifted result + fpcmpde{8,16,32}shl - Partitioned Unsigned Range Compare, with shifted result + fpcmpur{8,16,32}shl - 64-bit shifts on Floating-Point registers + fps{ll,ra,rl}64x - Misaligned loads and stores + ldm{sh,uh,sw,uw,x,ux} + ldm{sh,uh,sw,uw,x,ux}a + ldmf{s,d} + ldmf{s,d}a + stm{h,w,x} + stm{h,w,x}a + stmf{s,d} + stmf{s,d}a - Oracle Numbers + on{add,sub,mul,div} - Reverse Bytes/Bits + revbitsb + revbytes{h,w,x} - Run-Length instructions + rle_burst + rle_length - New crypto instructions + sha3 - Instruction to read the new register %entropy + rd %entropy New Alternate Address Identifiers: - 0x24, #ASI_CORE_COMMIT_COUNT - 0x24, #ASI_CORE_SELECT_COUNT - 0x48, #ASI_ARF_ECC_REG - 0x53, #ASI_ITLB_PROBE - 0x58, #ASI_DSFAR - 0x5a, #ASI_DTLB_PROBE_PRIMARY - 0x5b, #ASI_DTLB_PROBE_REAL - 0x64, #ASI_CORE_SELECT_COMMIT_NHT The new assembler command-line options for selecting the M8 architecture are: -Av9m8 or -Asparc6 for 64-bit binaries. -Av8plusm8 for 32-bit (v8+) binaries. The corresponding disassembler command-line options are: -msparc:v9m8 for 64-bit binaries. -msparc:v8plusm8 for 32-bit (v8+) binaries. Tested for regressions in the following targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux bfd/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v9m8): Define. (bfd_mach_sparc_v8plusm8): Likewise. (bfd_mach_sparc_v9_p): Adjust to M8. (bfd_mach_sparc_64bit_p): Likewise. * aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and bfd_mach_sparc_v8plusm8. * bfd-in2.h: Regenerated. * cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and sparc:v8plusm8. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and SHA3. * elf32-sparc.c (elf32_sparc_final_write_processing): Handle bfd_mach_sparc_v8plusm8. binutils/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Mention the SPARC M8 support. gas/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6', `v9m8' and `v8plusm8'. (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8. (get_hwcap_name): Support the M8 hardware capabilities. (sparc_ip): Handle new operand types. * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and -Asparc6, and the corresponding -xarch aliases. * testsuite/gas/sparc/sparc6.s: New file. * testsuite/gas/sparc/sparc6.d: Likewise. * testsuite/gas/sparc/sparc6-diag.s: Likewise. * testsuite/gas/sparc/sparc6-diag.l: Likewise. * testsuite/gas/sparc/fpcmpshl.s: Likewise. * testsuite/gas/sparc/fpcmpshl.d: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise. * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise. * testsuite/gas/sparc/ldm-stm.s: Likewise. * testsuite/gas/sparc/ldm-stm.d: Likewise. * testsuite/gas/sparc/ldm-stm-diag.s: Likewise. * testsuite/gas/sparc/ldm-stm-diag.l: Likewise. * testsuite/gas/sparc/ldmf-stmf.s: Likewise. * testsuite/gas/sparc/ldmf-stmf.d: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise. * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise. * testsuite/gas/sparc/on.s: Likewise. * testsuite/gas/sparc/on.d: Likewise. * testsuite/gas/sparc/on-diag.s: Likewise. * testsuite/gas/sparc/on-diag.l: Likewise. * testsuite/gas/sparc/rle.s: Likewise. * testsuite/gas/sparc/rle.d: Likewise. * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests. * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY. * testsuite/gas/sparc/rdasr.d: Likewise. include/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define. (ELF_SPARC_HWCAP2_ONADDSUB): Likewise. (ELF_SPARC_HWCAP2_ONMUL): Likewise. (ELF_SPARC_HWCAP2_ONDIV): Likewise. (ELF_SPARC_HWCAP2_DICTUNP): Likewise. (ELF_SPARC_HWCAP2_FPCMPSHL): Likewise. (ELF_SPARC_HWCAP2_RLE): Likewise. (ELF_SPARC_HWCAP2_SHA3): Likewise. * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8 and adjust SPARC_OPCODE_ARCH_MAX. (HWCAP2_SPARC6): Define. (HWCAP2_ONADDSUB): Likewise. (HWCAP2_ONMUL): Likewise. (HWCAP2_ONDIV): Likewise. (HWCAP2_DICTUNP): Likewise. (HWCAP2_FPCMPSHL): Likewise. (HWCAP2_RLE): Likewise. (HWCAP2_SHA3): Likewise. (OPM): Likewise. (OPMI): Likewise. (ONFCN): Likewise. (REVFCN): Likewise. (SIMM10): Likewise. opcodes/ChangeLog: 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. (X_IMM2): Define. (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8. (print_insn_sparc): Handle new operand types. * sparc-opc.c (MASK_M8): Define. (v6): Add MASK_M8. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Likewise. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (v9andleon): Likewise. (m8): Define. (HWS_VM8): Define. (HWS2_VM8): Likewise. (sparc_opcode_archs): Add entry for "m8". (sparc_opcodes): Add OSA2017 and M8 instructions dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, fpx{ll,ra,rl}64x, ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, ASI_CORE_SELECT_COMMIT_NHT.
Diffstat (limited to 'opcodes/sparc-dis.c')
-rw-r--r--opcodes/sparc-dis.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 739deb1..1742bb1 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -33,7 +33,8 @@
| (1 << SPARC_OPCODE_ARCH_V9D) \
| (1 << SPARC_OPCODE_ARCH_V9E) \
| (1 << SPARC_OPCODE_ARCH_V9V) \
- | (1 << SPARC_OPCODE_ARCH_V9M))
+ | (1 << SPARC_OPCODE_ARCH_V9M) \
+ | (1 << SPARC_OPCODE_ARCH_M8))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
@@ -128,6 +129,7 @@ static char *v9a_asr_reg_names[] =
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
#define X_IMM22(i) X_DISP22 (i)
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+#define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1))
/* These are for v9. */
#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
@@ -261,6 +263,9 @@ compute_arch_mask (unsigned long mach)
case bfd_mach_sparc_v8plusm :
case bfd_mach_sparc_v9m :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
+ case bfd_mach_sparc_v8plusm8 :
+ case bfd_mach_sparc_v9m8 :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8);
}
abort ();
}
@@ -653,6 +658,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
+ case ';': /* Double/even multiple of 8 doubles. */
fregx (X_RS1 (insn));
break;
@@ -661,6 +667,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
+ case ':': /* Double/even multiple of 8 doubles. */
fregx (X_RS2 (insn));
break;
@@ -679,6 +686,15 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
case '}': /* Double/even. */
fregx (X_RD (insn));
break;
+
+ case '^': /* Double/even multiple of 8 doubles. */
+ fregx (X_RD (insn) & ~0x6);
+ break;
+
+ case '\'': /* Double/even in FPCMPSHL. */
+ fregx (X_RS2 (insn | 0x11));
+ break;
+
#undef freg
#undef fregx
@@ -818,6 +834,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
(*info->fprintf_func) (stream, "%%mcdper");
break;
+ case '&':
+ (*info->fprintf_func) (stream, "%%entropy");
+ break;
+
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
@@ -969,6 +989,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
+ X_ASI (insn)));
break;
+ case '|': /* 2-bit immediate */
+ (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn));
+ break;
+
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;