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author | Neal Frager <neal.frager@amd.com> | 2023-10-05 13:51:03 +0100 |
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committer | Michael J. Eager <eager@eagercon.com> | 2023-10-06 10:53:45 -0700 |
commit | 6bbf249557ba17cfebe01c67370df4da9e6a56f9 (patch) | |
tree | b1242471838ab0e7131aec8879013c258ef8a992 /opcodes/microblaze-opcm.h | |
parent | 9a896be33224654760c46d3698218241d0a1f354 (diff) | |
download | gdb-6bbf249557ba17cfebe01c67370df4da9e6a56f9.zip gdb-6bbf249557ba17cfebe01c67370df4da9e6a56f9.tar.gz gdb-6bbf249557ba17cfebe01c67370df4da9e6a56f9.tar.bz2 |
opcodes: microblaze: Add new bit-field instructions
This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.
Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:
https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils
Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
Diffstat (limited to 'opcodes/microblaze-opcm.h')
-rw-r--r-- | opcodes/microblaze-opcm.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index c91b002..3c4f894 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -29,7 +29,7 @@ enum microblaze_instr addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu, swapb, swaph, idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, - ncget, ncput, muli, bslli, bsrai, bsrli, mului, + ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, /* 'or/and/xor' are C++ keywords. */ microblaze_or, microblaze_and, microblaze_xor, andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, @@ -130,6 +130,7 @@ enum microblaze_instr_type #define RB_LOW 11 /* Low bit for RB. */ #define IMM_LOW 0 /* Low bit for immediate. */ #define IMM_MBAR 21 /* low bit for mbar instruction. */ +#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ #define RD_MASK 0x03E00000 #define RA_MASK 0x001F0000 @@ -142,6 +143,9 @@ enum microblaze_instr_type /* Imm mask for mbar. */ #define IMM5_MBAR_MASK 0x03E00000 +/* Imm mask for extract/insert width. */ +#define IMM5_WIDTH_MASK 0x000007C0 + /* FSL imm mask for get, put instructions. */ #define RFSL_MASK 0x000000F |