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authorDJ Delorie <dj@redhat.com>2009-06-24 03:06:42 +0000
committerDJ Delorie <dj@redhat.com>2009-06-24 03:06:42 +0000
commitdab97f2471e9939e4ddd126a5cab730c5f6831b5 (patch)
treefc89c5e5026a1086040665bef480e432aa032cda /opcodes/mep-opc.c
parent378a0c07cab0852b72230e3a16a66d5d8108af51 (diff)
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[cgen]
* intrinsics.scm: Updates to support IVC2. (belongs-to-group?): Check IVC2 slots. (-slots-attribute): New. (targets::attributes): Add SLOTS. (target:add-well-known-intrinsics): Add CPMOV. (md-insn): Add CPTYPE and CRET?. (add-md-insn): Likewise. (add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has duplicate insns with different bit patterns. (write-cgen-insn?): Add cret? support. (intrinsics.h): Add vector types. (runtime-op): Add vector support. (intrinsic-protos.h): Let GCC define its types. Add cret? support. * cpu/mep-core.cpu: Add CPTYPE and CRET attributes. * cpu/mep-ivc2.cpu: Update all insns to include type information. (h-cr-ivc2): Default to typeless. (h-ccr-ivc2): Fix register width. (SLOTS): Fix values and default. (ivc2_*): Add control register names. (crop, crqp, crpp, croc, crqc, crpc): Default to typeless. [opcodes] * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. [sid/component/cgen-cpu/mep] * ivc2-cop.cxx (ivc2_cphadd_w): Change to return value. (ivc2_cpsubaca0u_b): Remove debug line. * ivc2-cpu.h (ivc2_cpccadd_b): Change to return value. * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-32-decode.cxx: Regenerate. * mep-cop1-32-sem.cxx: Regenerate. * mep-cop1-48-decode.cxx: Regenerate. * mep-cop1-48-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. * mep-core1-decode.cxx: Regenerate. * mep-cpu.h: Regenerate. * mep-decode.cxx: Regenerate. * mep-desc.h: Regenerate.
Diffstat (limited to 'opcodes/mep-opc.c')
-rw-r--r--opcodes/mep-opc.c32
1 files changed, 19 insertions, 13 deletions
diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index aa6c093..75a10f7 100644
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -145,6 +145,12 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
int ok1;
int ok2;
int ok3;
+
+ /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
+ can't relax that. The 24-bit BSR is matched instead. */
+ if (insn->base->num == MEP_INSN_BSR12
+ && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
+ return 0;
/* If the insn has an option bit set that we don't want,
reject it. */
@@ -6173,67 +6179,67 @@ static const CGEN_IBASE mep_cgen_macro_insn_table[] =
/* nop */
{
-1, "nop", "nop", 16,
- { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rnc,$zero($rma) */
{
-1, "sb16-0", "sb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rns,$zero($rma) */
{
-1, "sh16-0", "sh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,$zero($rma) */
{
-1, "sw16-0", "sw", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rnc,$zero($rma) */
{
-1, "lb16-0", "lb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rns,$zero($rma) */
{
-1, "lh16-0", "lh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,$zero($rma) */
{
-1, "lw16-0", "lw", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rnuc,$zero($rma) */
{
-1, "lbu16-0", "lbu", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rnus,$zero($rma) */
{
-1, "lhu16-0", "lhu", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcp $crn,$zero($rma) */
{
-1, "swcp16-0", "swcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcp $crn,$zero($rma) */
{
-1, "lwcp16-0", "lwcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcp $crn64,$zero($rma) */
{
-1, "smcp16-0", "smcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcp $crn64,$zero($rma) */
{
-1, "lmcp16-0", "lmcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
};