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authorDJ Delorie <dj@redhat.com>2009-05-22 17:37:45 +0000
committerDJ Delorie <dj@redhat.com>2009-05-22 17:37:45 +0000
commit1d74713bc6983fddbae51aed5337c0b88b0a672f (patch)
tree04746389866a2bc40caf9dfd7e5efd3ed24251a2 /opcodes/mep-opc.c
parentc1e679ec0a47d39a315c7adb5e28106fcb27beac (diff)
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[cgen]
* cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder. (mep_config_map): Regenerate. * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as ivc2-specific names. (simm8p20): New. (cmovc): move to after field definitions, use ivc2-specific register names. (cpmovi_b_P0S_P1): New. [utils/mep] * mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW size to default configuration. [sid/component/cgen-cpu/mep] * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-decode.h: Regenerate. * mep-cop1-16-model.cxx: Regenerate. * mep-cop1-16-model.h: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-decode.h: Regenerate. * mep-cop1-64-model.cxx: Regenerate. * mep-cop1-64-model.h: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.
Diffstat (limited to 'opcodes/mep-opc.c')
-rw-r--r--opcodes/mep-opc.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index 7bf92b6..1a8321e 100644
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -92,7 +92,7 @@ mep_config_map_struct mep_config_map[] =
{
/* config-map-start */
/* Default entry: first module, with all options enabled. */
- { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,1, 0, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) },
+ { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) },
{ "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" },
0
| (1 << CGEN_INSN_OPTIONAL_CP_INSN)
@@ -558,6 +558,10 @@ static const CGEN_IFMT ifmt_cpmoviu_w_P0_P1 ATTRIBUTE_UNUSED = {
32, 32, 0xf8300f, { { F (F_IVC2_IMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } }
};
+static const CGEN_IFMT ifmt_cpmovi_b_P0S_P1 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfff8300f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_8U20) }, { F (F_IVC2_4U28) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_cpfmulia1s0u_b_P1 ATTRIBUTE_UNUSED = {
32, 32, 0xf801ff, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } }
};
@@ -1951,16 +1955,16 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RM), ',', OP (CRNX64), 0 } },
& ifmt_cmov_crn_rm, { 0xf007f001 }
},
-/* cmovc $ccrn,$rm */
+/* cmovc $ivc2c3ccrn,$rm */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (CCRN), ',', OP (RM), 0 } },
+ { { MNEM, ' ', OP (IVC2C3CCRN), ',', OP (RM), 0 } },
& ifmt_cmovc_ccrn_rm, { 0xf007f002 }
},
-/* cmovc $rm,$ccrn */
+/* cmovc $rm,$ivc2c3ccrn */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RM), ',', OP (CCRN), 0 } },
+ { { MNEM, ' ', OP (RM), ',', OP (IVC2C3CCRN), 0 } },
& ifmt_cmovc_ccrn_rm, { 0xf007f003 }
},
/* cmovh $crnx64,$rm */
@@ -5287,6 +5291,12 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, 0 } },
& ifmt_c0nop_P0_P0S, { 0x0 }
},
+/* cpmovi.b $crqp,$simm8p20 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (CRQP), ',', OP (SIMM8P20), 0 } },
+ & ifmt_cpmovi_b_P0S_P1, { 0xb00000 }
+ },
/* cpadda1u.b $crqp,$crpp */
{
{ 0, 0, 0, 0 },