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authorAlan Modra <amodra@gmail.com>2002-12-02 13:13:37 +0000
committerAlan Modra <amodra@gmail.com>2002-12-02 13:13:37 +0000
commit6a51a8a8d34f57a9b88de4961c67d0a4cb7026e3 (patch)
tree2188ef42e5ae09fc9a9238f35d54564ef9779ba5 /opcodes/mcore-dis.c
parent4c83186b7629c3e0645034df71a9ae4ac77e1e8a (diff)
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* arm-dis.c (print_insn_arm): Constify "insn". Formatting.
(print_insn_thumb): Likewise. * h8500-dis.c (print_insn_h8500): Constify "opcode". * mcore-dis.c (print_insn_mcore): Constify "op". Formatting. * ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid type-punned pointer warnings. <case 'L'>: Likewise. Fix error message too. * pdp11-dis.c (print_reg): Warning fix. * sh-dis.c (print_movxy): Constify "op" param. (print_insn_ddt): Constify sh_opcode_info vars. (print_insn_ppi): Likewise. (print_insn_sh): Likewise. * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid type-punned pointer warnings. * w65-dis.c (print_insn_w65): Constify "op".
Diffstat (limited to 'opcodes/mcore-dis.c')
-rw-r--r--opcodes/mcore-dis.c78
1 files changed, 57 insertions, 21 deletions
diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index ad45318..ba33dd3 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -1,5 +1,5 @@
/* Disassemble Motorola M*Core instructions.
- Copyright 1993, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1993, 1999, 2000, 2002 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -89,12 +89,12 @@ print_insn_mcore (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
- unsigned char ibytes[4];
- fprintf_ftype fprintf = info->fprintf_func;
- void * stream = info->stream;
- unsigned short inst;
- mcore_opcode_info * op;
- int status;
+ unsigned char ibytes[4];
+ fprintf_ftype fprintf = info->fprintf_func;
+ void *stream = info->stream;
+ unsigned short inst;
+ const mcore_opcode_info *op;
+ int status;
info->bytes_per_chunk = 2;
@@ -128,19 +128,48 @@ print_insn_mcore (memaddr, info)
switch (op->opclass)
{
- case O0: break;
- case OT: fprintf (stream, "\t%d", inst & 0x3); break;
+ case O0:
+ break;
+
+ case OT:
+ fprintf (stream, "\t%d", inst & 0x3);
+ break;
+
case O1:
case JMP:
- case JSR: fprintf (stream, "\t%s", name); break;
- case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
- case O1R1: fprintf (stream, "\t%s, r1", name); break;
+ case JSR:
+ fprintf (stream, "\t%s", name);
+ break;
+
+ case OC:
+ fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
+ break;
+
+ case O1R1:
+ fprintf (stream, "\t%s, r1", name);
+ break;
+
case MULSH:
- case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
- case X1: fprintf (stream, "\tr1, %s", name); break;
- case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
- case RM: fprintf (stream, "\t%s-r15, (r0)", name); break;
- case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break;
+ case O2:
+ fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
+ break;
+
+ case X1:
+ fprintf (stream, "\tr1, %s", name);
+ break;
+
+ case OI:
+ fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
+ break;
+
+ case RM:
+ fprintf (stream, "\t%s-r15, (r0)", name);
+ break;
+
+ case RQ:
+ fprintf (stream, "\tr4-r7, (%s)", name);
+ break;
+
case OB:
case OBRa:
case OBRb:
@@ -149,10 +178,17 @@ print_insn_mcore (memaddr, info)
case SIa:
case OMa:
case OMb:
- case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break;
- case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break;
- case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
- name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
+ case OMc:
+ fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
+ break;
+
+ case I7:
+ fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
+ break;
+
+ case LS:
+ fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
+ name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
break;
case BR: