diff options
| author | Jan Beulich <jbeulich@suse.com> | 2019-11-08 09:04:53 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-11-08 09:04:53 +0100 |
| commit | 4a5c67ed841db42c7be13cb2991ece3b3fc4bf75 (patch) | |
| tree | 1fd1a44252fd896a35508f621c16725163ecd844 /opcodes/i386-reg.tbl | |
| parent | 00cee14fbad24453ff56656c5726ef5e4b0de588 (diff) | |
| download | gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.zip gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.tar.gz gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.tar.bz2 | |
x86: convert Control/Debug/Test from bitfield to enumerator
This is to further shrink the operand type representation.
Diffstat (limited to 'opcodes/i386-reg.tbl')
| -rw-r--r-- | opcodes/i386-reg.tbl | 112 |
1 files changed, 56 insertions, 56 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 4c2523b..5d6dc53 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -113,64 +113,64 @@ fs, Class=SReg, 0, 4, 44, 54 gs, Class=SReg, 0, 5, 45, 55 flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval // Control registers. -cr0, Control, 0, 0, Dw2Inval, Dw2Inval -cr1, Control, 0, 1, Dw2Inval, Dw2Inval -cr2, Control, 0, 2, Dw2Inval, Dw2Inval -cr3, Control, 0, 3, Dw2Inval, Dw2Inval -cr4, Control, 0, 4, Dw2Inval, Dw2Inval -cr5, Control, 0, 5, Dw2Inval, Dw2Inval -cr6, Control, 0, 6, Dw2Inval, Dw2Inval -cr7, Control, 0, 7, Dw2Inval, Dw2Inval -cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval -cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval -cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval -cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval -cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval -cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval -cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval -cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval +cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval +cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval +cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval +cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval +cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval +cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval +cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval +cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval +cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval +cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval +cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval +cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval +cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval +cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval +cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval +cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval // Debug registers. -db0, Debug, 0, 0, Dw2Inval, Dw2Inval -db1, Debug, 0, 1, Dw2Inval, Dw2Inval -db2, Debug, 0, 2, Dw2Inval, Dw2Inval -db3, Debug, 0, 3, Dw2Inval, Dw2Inval -db4, Debug, 0, 4, Dw2Inval, Dw2Inval -db5, Debug, 0, 5, Dw2Inval, Dw2Inval -db6, Debug, 0, 6, Dw2Inval, Dw2Inval -db7, Debug, 0, 7, Dw2Inval, Dw2Inval -db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval -db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval -db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval -db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval -db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval -db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval -db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval -db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval -dr0, Debug, 0, 0, Dw2Inval, Dw2Inval -dr1, Debug, 0, 1, Dw2Inval, Dw2Inval -dr2, Debug, 0, 2, Dw2Inval, Dw2Inval -dr3, Debug, 0, 3, Dw2Inval, Dw2Inval -dr4, Debug, 0, 4, Dw2Inval, Dw2Inval -dr5, Debug, 0, 5, Dw2Inval, Dw2Inval -dr6, Debug, 0, 6, Dw2Inval, Dw2Inval -dr7, Debug, 0, 7, Dw2Inval, Dw2Inval -dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval -dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval -dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval -dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval -dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval -dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval -dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval -dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval +db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval +db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval +db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval +db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval +db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval +db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval +db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval +db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval +db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval +db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval +db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval +db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval +db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval +db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval +db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval +db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval +dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval +dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval +dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval +dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval +dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval +dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval +dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval +dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval +dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval +dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval +dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval +dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval +dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval +dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval +dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval +dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval // Test registers. -tr0, Test, 0, 0, Dw2Inval, Dw2Inval -tr1, Test, 0, 1, Dw2Inval, Dw2Inval -tr2, Test, 0, 2, Dw2Inval, Dw2Inval -tr3, Test, 0, 3, Dw2Inval, Dw2Inval -tr4, Test, 0, 4, Dw2Inval, Dw2Inval -tr5, Test, 0, 5, Dw2Inval, Dw2Inval -tr6, Test, 0, 6, Dw2Inval, Dw2Inval -tr7, Test, 0, 7, Dw2Inval, Dw2Inval +tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval +tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval +tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval +tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval +tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval +tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval +tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval +tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval // MMX and simd registers. mm0, RegMMX, 0, 0, 29, 41 mm1, RegMMX, 0, 1, 30, 42 |