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authorJan Beulich <jbeulich@suse.com>2019-11-08 09:04:09 +0100
committerJan Beulich <jbeulich@suse.com>2019-11-08 09:04:09 +0100
commit00cee14fbad24453ff56656c5726ef5e4b0de588 (patch)
tree1b4bbeafdf3970582fbe95e092b178bacf070cd2 /opcodes/i386-reg.tbl
parentbab6aec1255ba2ec8de3ae0363958e2ff26ce25d (diff)
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x86: convert SReg from bitfield to enumerator
This is to further shrink the operand type representation.
Diffstat (limited to 'opcodes/i386-reg.tbl')
-rw-r--r--opcodes/i386-reg.tbl14
1 files changed, 7 insertions, 7 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 8e6a2df..4c2523b 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -105,13 +105,13 @@ k5, RegMask, 0, 5, 98, 123
k6, RegMask, 0, 6, 99, 124
k7, RegMask, 0, 7, 100, 125
// Segment registers.
-es, SReg, 0, 0, 40, 50
-cs, SReg, 0, 1, 41, 51
-ss, SReg, 0, 2, 42, 52
-ds, SReg, 0, 3, 43, 53
-fs, SReg, 0, 4, 44, 54
-gs, SReg, 0, 5, 45, 55
-flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
+es, Class=SReg, 0, 0, 40, 50
+cs, Class=SReg, 0, 1, 41, 51
+ss, Class=SReg, 0, 2, 42, 52
+ds, Class=SReg, 0, 3, 43, 53
+fs, Class=SReg, 0, 4, 44, 54
+gs, Class=SReg, 0, 5, 45, 55
+flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
// Control registers.
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
cr1, Control, 0, 1, Dw2Inval, Dw2Inval