ubsan: crx: left shift cannot be represented in type 'int'

The ubsan complaint is fixed by the SBM change, with similar possible
complaints fixed by the EXTRACT change.  The rest is just cleanup.

include/
	* opcode/crx.h (inst <match>): Make unsigned int.
opcodes/
	* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
	(get_number_of_operands, getargtype, getbits, getregname),
	(getcopregname, getprocregname, gettrapstring, getcinvstring),
	(getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
	(powerof2, match_opcode, make_instruction, print_arguments),
	(print_arg): Delete forward declarations, moving static to..
	(getregname, getcopregname, getregliststring): ..these definitions.
	(build_mask): Return unsigned int mask.
	(match_opcode): Use unsigned int vars.

1 files changed, 9 insertions, 27 deletions

diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c
index 4abc7d2..3834748 100644
--- a/opcodes/crx-dis.c
+++ b/opcodes/crx-dis.c
@@ -31,11 +31,10 @@
 
 /* Extract 'n_bits' from 'a' starting from offset 'offs'.  */
 #define EXTRACT(a, offs, n_bits)	    \
-  (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL)   \
-  : (((a) >> (offs)) & ((1 << (n_bits)) -1)))
+  (((a) >> (offs)) & ((2ull << (n_bits - 1)) - 1))
 
 /* Set Bit Mask - a mask to set all bits starting from offset 'offs'.  */
-#define SBM(offs)  ((((1 << (32 - offs)) -1) << (offs)))
+#define SBM(offs)  ((-1u << (offs)) & 0xffffffff)
 
 typedef unsigned long dwordU;
 typedef unsigned short wordU;
@@ -98,23 +97,6 @@ static int cst4flag;
    incremented (escape sequence is used).  */
 static int size_changed;
 
-static int get_number_of_operands (void);
-static argtype getargtype     (operand_type);
-static int getbits	      (operand_type);
-static char *getregname	      (reg);
-static char *getcopregname    (copreg, reg_type);
-static char * getprocregname  (int);
-static char *gettrapstring    (unsigned);
-static char *getcinvstring    (unsigned);
-static void getregliststring  (int, char *, enum REG_ARG_TYPE);
-static wordU get_word_at_PC   (bfd_vma, struct disassemble_info *);
-static void get_words_at_PC   (bfd_vma, struct disassemble_info *);
-static unsigned long build_mask (void);
-static int powerof2	      (int);
-static int match_opcode	      (void);
-static void make_instruction  (void);
-static void print_arguments   (ins *, bfd_vma, struct disassemble_info *);
-static void print_arg	      (argument *, bfd_vma, struct disassemble_info *);
 
 /* Retrieve the number of operands for the current assembled instruction.  */
 
@@ -183,7 +165,7 @@ getcinvstring (unsigned int num)
 
 /* Given a register enum value, retrieve its name.  */
 
-char *
+static char *
 getregname (reg r)
 {
   const reg_entry * regentry = &crx_regtab[r];
@@ -196,7 +178,7 @@ getregname (reg r)
 
 /* Given a coprocessor register enum value, retrieve its name.  */
 
-char *
+static char *
 getcopregname (copreg r, reg_type type)
 {
   const reg_entry * regentry;
@@ -241,7 +223,7 @@ powerof2 (int x)
 
 /* Transform a register bit mask to a register list.  */
 
-void
+static void
 getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
 {
   char temp_string[16];
@@ -315,11 +297,11 @@ makelongparameter (ULONGLONG val, int start, int end)
 /* Build a mask of the instruction's 'constant' opcode,
    based on the instruction's printing flags.  */
 
-static unsigned long
+static unsigned int
 build_mask (void)
 {
   unsigned int print_flags;
-  unsigned long mask;
+  unsigned int mask;
 
   print_flags = instruction->flags & FMT_CRX;
   switch (print_flags)
@@ -352,10 +334,10 @@ build_mask (void)
 static int
 match_opcode (void)
 {
-  unsigned long mask;
+  unsigned int mask;
 
   /* The instruction 'constant' opcode doewsn't exceed 32 bits.  */
-  unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
+  unsigned int doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
 
   /* Start searching from end of instruction table.  */
   instruction = &crx_instruction[NUMOPCODES - 2];