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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:18:57 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:30:33 +0100 |
| commit | e5d6e09ee6cea13942a8042945e784f483a6f3af (patch) | |
| tree | 682983efcb6e4ceb1ec5cbebfbb196abaebf3b94 /opcodes/arm-dis.c | |
| parent | e2b0ab597857bfe9d7c8742ff50bbb77c70936c4 (diff) | |
| download | gdb-e5d6e09ee6cea13942a8042945e784f483a6f3af.zip gdb-e5d6e09ee6cea13942a8042945e784f483a6f3af.tar.gz gdb-e5d6e09ee6cea13942a8042945e784f483a6f3af.tar.bz2 | |
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 0ed893b..4a5609a 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2714,6 +2714,7 @@ static const struct opcode16 thumb_opcodes[] = %E print the lsb and width fields of a bfc/bfi instruction %F print the lsb and width fields of a sbfx/ubfx instruction %G print a fallback offset for Branch Future instructions + %W print an offset for BF instruction %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction @@ -5870,6 +5871,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'W': + { + unsigned int immA = (given & 0x001f0000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x10000) ? offset - (1 << 17) : offset; + + info->print_address_func (pc + 4 + offset, info); + } + break; + case 'b': { unsigned int S = (given & 0x04000000u) >> 26; |