diff options
| author | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:20:48 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:20:48 +0100 |
| commit | ba6cd17f0a28e54d9b4ef46397d448f1d208d9a0 (patch) | |
| tree | 18c44358148197dc435b153c1b6f730135971ee3 /opcodes/arm-dis.c | |
| parent | e39c1607a2df3a97bf7b70bef6de5b7a2db55eea (diff) | |
| download | gdb-ba6cd17f0a28e54d9b4ef46397d448f1d208d9a0.zip gdb-ba6cd17f0a28e54d9b4ef46397d448f1d208d9a0.tar.gz gdb-ba6cd17f0a28e54d9b4ef46397d448f1d208d9a0.tar.bz2 | |
[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions
This patch makes changes to the <spec_reg> operand for VMRS and VMSR
instructions as per the Armv8.1-M Mainline.
New <spec_reg> options to support are:
0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags.
0b1100: VPR, privileged only access to the VPR register.
0b1101: P0, access to VPR.P0 predicate fields
0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating
point context.
0b1111: FPCXT_S, enables saving and restoring of Secure floating point
context
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ad65ffa..0503d93 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -809,8 +809,10 @@ static const struct sopcode32 coprocessor_opcodes[] = /* Floating point coprocessor (VFP) instructions. */ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE), 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), @@ -823,12 +825,22 @@ static const struct sopcode32 coprocessor_opcodes[] = 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, + {ANY, ARM_FEATURE_COPROC (FPU_MVE), + 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_MVE), + 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, - {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE), 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), @@ -841,6 +853,14 @@ static const struct sopcode32 coprocessor_opcodes[] = 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, + {ANY, ARM_FEATURE_COPROC (FPU_MVE), + 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"}, + {ANY, ARM_FEATURE_COPROC (FPU_MVE), + 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |