[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers

GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.

Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().

A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.

ChangeLog entries are as follows:

*** bfd/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
	relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.

*** gas/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/tc-arm.c (parse_sys_vldr_vstr): New function.
	(OP_VLDR): New enum operand_parse_code enumerator.
	(parse_operands): Add logic for OP_VLDR.
	(do_t_vldr_vstr_sysreg): New function.
	(do_vldr_vstr): Likewise.
	(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
	(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
	Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
	uses of VLDR and VSTR.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
	above bad uses.
	* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
	VSTR valid uses.
	* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
	above examples.

*** opcodes/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	specifier.  Add entries for VLDR and VSTR of system registers.
	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
	of %J and %K format specifier.

1 files changed, 51 insertions, 1 deletions

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ea053a3..c2a8a5f 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -111,6 +111,8 @@ struct opcode16
    %B			print vstm/vldm register list
    %C			print vscclrm register list
    %I                   print cirrus signed shift immediate: bits 0..3|4..6
+   %J			print register for VLDR instruction
+   %K			print address for VLDR instruction
    %F			print the COUNT field of a LFM/SFM instruction.
    %P			print floating point precision in arithmetic insn
    %Q			print floating point precision in ldf/stf insn
@@ -471,6 +473,10 @@ static const struct sopcode32 coprocessor_opcodes[] =
     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
+  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+    0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
+  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+    0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
@@ -3462,6 +3468,8 @@ print_insn_coprocessor (bfd_vma pc,
   int cp_num;
   struct arm_private_data *private_data = info->private_data;
   arm_feature_set allowed_arches = ARM_ARCH_NONE;
+  arm_feature_set arm_ext_v8_1m_main =
+    ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
 
   allowed_arches = private_data->features;
 
@@ -3557,23 +3565,34 @@ print_insn_coprocessor (bfd_vma pc,
 	  /* Floating-point instructions.  */
 	  if (cp_num == 9 || cp_num == 10 || cp_num == 11)
 	    continue;
+
+	  /* Armv8.1-M Mainline FP & MVE instructions.  */
+	  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
+	      && !ARM_CPU_IS_ANY (allowed_arches)
+	      && (cp_num == 8 || cp_num == 14 || cp_num == 15))
+	    continue;
 	}
 
       for (c = insn->assembler; *c; c++)
 	{
 	  if (*c == '%')
 	    {
-	      switch (*++c)
+	      const char mod = *++c;
+	      switch (mod)
 		{
 		case '%':
 		  func (stream, "%%");
 		  break;
 
 		case 'A':
+		case 'K':
 		  {
 		    int rn = (given >> 16) & 0xf;
 		    bfd_vma offset = given & 0xff;
 
+		    if (mod == 'K')
+		      offset = given & 0x7f;
+
 		    func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
 
 		    if (PRE_BIT_SET || WRITEBACK_BIT_SET)
@@ -3705,6 +3724,37 @@ print_insn_coprocessor (bfd_vma pc,
 
 		  break;
 
+		case 'J':
+		  {
+		    int regno = ((given >> 19) & 0x8) | ((given >> 13) & 0x7);
+
+		    switch (regno)
+		      {
+		      case 0x1:
+			func (stream, "FPSCR");
+			break;
+		      case 0x2:
+			func (stream, "FPSCR_nzcvqc");
+			break;
+		      case 0xc:
+			func (stream, "VPR");
+			break;
+		      case 0xd:
+			func (stream, "P0");
+			break;
+		      case 0xe:
+			func (stream, "FPCXTNS");
+			break;
+		      case 0xf:
+			func (stream, "FPCXTS");
+			break;
+		      default:
+			func (stream, "<invalid reg %d>", regno);
+			break;
+		      }
+		  }
+		  break;
+
 		case 'F':
 		  switch (given & 0x00408000)
 		    {