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author | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:11:08 +0100 |
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committer | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:11:08 +0100 |
commit | 23d00a419fe67801afc02a87f7ab9c5374b0238e (patch) | |
tree | cba7cb850ffd1f9e5a741ebbf0c40bb9031c89e8 /opcodes/arm-dis.c | |
parent | cd4797ee054654160fe6c4b6fbecd636b7961e19 (diff) | |
download | gdb-23d00a419fe67801afc02a87f7ab9c5374b0238e.zip gdb-23d00a419fe67801afc02a87f7ab9c5374b0238e.tar.gz gdb-23d00a419fe67801afc02a87f7ab9c5374b0238e.tar.bz2 |
[binutils, Arm] Add support for shift instructions in MVE
This patch adds the following instructions which are part of
Armv8.1-M MVE:
ASRL (imm)
ASRL (reg)
LSLL (imm)
LSLL (reg)
LSRL
SQRSHRL
SRQSHR
SQSHLL
SQSHL
SRSHRL
SRSHR
UQRSHLL
UQRSHL
UQSHLL
UQSHL
URSHLL
URSHL
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): New entries for
OP_RRnpcsp_I32 (register or integer operands).
(do_mve_scalar_shift): New.
(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
* testsuite/gas/arm/mve-shift.d: New.
* testsuite/gas/arm/mve-shift.s: New.
* testsuite/gas/arm/mve-shift-bad.d: New.
* testsuite/gas/arm/mve-shift-bad.s: New.
* testsuite/gas/arm/mve-shift-bad.l: New.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (emun mve_instructions): Updated for new instructions.
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
uqshl, urshrl and urshr.
(is_mve_okay_in_it): Add new instructions to TRUE list.
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
(print_insn_mve): Updated to accept new %j,
%<bitfield>m and %<bitfield>n patterns.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r-- | opcodes/arm-dis.c | 183 |
1 files changed, 183 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 096b571..ab99fb7 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -264,6 +264,23 @@ enum mve_instructions MVE_VREV16, MVE_VREV32, MVE_VREV64, + MVE_LSLL, + MVE_LSLLI, + MVE_LSRL, + MVE_ASRL, + MVE_ASRLI, + MVE_SQRSHRL, + MVE_SQRSHR, + MVE_UQRSHL, + MVE_UQRSHLL, + MVE_UQSHL, + MVE_UQSHLL, + MVE_URSHRL, + MVE_URSHR, + MVE_SRSHRL, + MVE_SRSHR, + MVE_SQSHLL, + MVE_SQSHL, MVE_NONE }; @@ -2026,6 +2043,7 @@ static const struct opcode32 neon_opcodes[] = %d print addr mode of MVE vldr[bhw] and vstr[bhw] %u print 'U' (unsigned) or 'S' for various mve instructions %i print MVE predicate(s) for vpt and vpst + %j print a 5-bit immediate from hw2[14:12,7:6] %m print rounding mode for vcvt and vrint %n print vector comparison code for predicated instruction %s print size for various vcvt instructions @@ -2046,6 +2064,8 @@ static const struct opcode32 neon_opcodes[] = %<bitfield>F print as a MVE S register %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is UNPREDICTABLE + + %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE %<bitfield>s print size for vector predicate & non VMOV instructions %<bitfield>I print carry flag or not %<bitfield>i print immediate for vstr/vldr reg +/- imm @@ -3295,6 +3315,91 @@ static const struct mopcode32 mve_opcodes[] = 0xee011f40, 0xff811f70, "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_ASRLI, + 0xea50012f, 0xfff1813f, + "asrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_ASRL, + 0xea50012d, 0xfff101ff, + "asrl%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_LSLLI, + 0xea50010f, 0xfff1813f, + "lsll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_LSLL, + 0xea50010d, 0xfff101ff, + "lsll%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_LSRL, + 0xea50011f, 0xfff1813f, + "lsrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SQRSHRL, + 0xea51012d, 0xfff101ff, + "sqrshrl%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SQRSHR, + 0xea500f2d, 0xfff00fff, + "sqrshr%c\t%16-19S, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SQSHLL, + 0xea51013f, 0xfff1813f, + "sqshll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SQSHL, + 0xea500f3f, 0xfff08f3f, + "sqshl%c\t%16-19S, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SRSHRL, + 0xea51012f, 0xfff1813f, + "srshrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_SRSHR, + 0xea500f2f, 0xfff08f3f, + "srshr%c\t%16-19S, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_UQRSHLL, + 0xea51010d, 0xfff101ff, + "uqrshll%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_UQRSHL, + 0xea500f0d, 0xfff00fff, + "uqrshl%c\t%16-19S, %12-15S"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_UQSHLL, + 0xea51010f, 0xfff1813f, + "uqshll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_UQSHL, + 0xea500f0f, 0xfff08f3f, + "uqshl%c\t%16-19S, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_URSHRL, + 0xea51011f, 0xfff1813f, + "urshrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_COPROC (FPU_MVE), + MVE_URSHR, + 0xea500f1f, 0xfff08f3f, + "urshr%c\t%16-19S, %j"}, + {ARM_FEATURE_CORE_LOW (0), MVE_NONE, 0x00000000, 0x00000000, 0} @@ -5169,6 +5274,23 @@ is_mve_okay_in_it (enum mve_instructions matched_insn) case MVE_VMOV2_VEC_LANE_TO_GP: case MVE_VMOV2_GP_TO_VEC_LANE: case MVE_VMOV_VEC_LANE_TO_GP: + case MVE_LSLL: + case MVE_LSLLI: + case MVE_LSRL: + case MVE_ASRL: + case MVE_ASRLI: + case MVE_SQRSHRL: + case MVE_SQRSHR: + case MVE_UQRSHL: + case MVE_UQRSHLL: + case MVE_UQSHL: + case MVE_UQSHLL: + case MVE_URSHRL: + case MVE_URSHR: + case MVE_SRSHRL: + case MVE_SRSHR: + case MVE_SQSHLL: + case MVE_SQSHL: return TRUE; default: return FALSE; @@ -5515,6 +5637,22 @@ is_mve_encoding_conflict (unsigned long given, else return FALSE; + case MVE_ASRLI: + case MVE_ASRL: + case MVE_LSLLI: + case MVE_LSLL: + case MVE_LSRL: + case MVE_SQRSHRL: + case MVE_SQSHLL: + case MVE_SRSHRL: + case MVE_UQRSHLL: + case MVE_UQSHLL: + case MVE_URSHRL: + if (arm_decode_field (given, 9, 11) == 0x7) + return TRUE; + else + return FALSE; + default: case MVE_VADD_FP_T1: case MVE_VADD_FP_T2: @@ -6490,6 +6628,34 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, return FALSE; } + case MVE_LSLL: + case MVE_LSLLI: + case MVE_LSRL: + case MVE_ASRL: + case MVE_ASRLI: + case MVE_UQSHLL: + case MVE_UQRSHLL: + case MVE_URSHRL: + case MVE_SRSHRL: + case MVE_SQSHLL: + case MVE_SQRSHRL: + { + unsigned long gpr = arm_decode_field (given, 9, 11); + gpr = ((gpr << 1) | 1); + if (gpr == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (gpr == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + default: return FALSE; } @@ -8983,6 +9149,15 @@ print_insn_mve (struct disassemble_info *info, long given) } break; + case 'j': + { + unsigned int imm5 = 0; + imm5 |= arm_decode_field (given, 6, 7); + imm5 |= (arm_decode_field (given, 12, 14) << 2); + func (stream, "#%u", (imm5 == 0) ? 32 : imm5); + } + break; + case 'n': print_vec_condition (info, given, insn->mve_op); break; @@ -9088,6 +9263,14 @@ print_insn_mve (struct disassemble_info *info, long given) else func (stream, "%s", arm_regnames[value]); break; + + case 'S': + if (value == 13 || value == 15) + is_unpredictable = TRUE; + else + func (stream, "%s", arm_regnames[value]); + break; + case 's': print_mve_size (info, value, |