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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:14:40 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:14:40 +0000
commit3c9017d2509dc3cd2bb621414a5ac61f59efaca8 (patch)
treea67f07721f3988e8ad043026280806ac714827d7 /opcodes/arm-dis.c
parent48adcd8ed515c2a4960713fc4ff3f98930062069 (diff)
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* gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
(do_sha1h): New function. (do_sha1su1): Likewise. (do_sha256su0): Likewise. (insns): Add 2 operand SHA instructions. * gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise. * opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r--opcodes/arm-dis.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 97a96d1..8a7dc0f 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -590,6 +590,9 @@ static const struct opcode32 neon_opcodes[] =
{FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
{FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
{FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},